Lecture 5: FPGAseecs151/sp20/files/lec5... · 2020. 2. 4. · EE141 21 Example Partition,...
Transcript of Lecture 5: FPGAseecs151/sp20/files/lec5... · 2020. 2. 4. · EE141 21 Example Partition,...
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EECS 151/251ASpring2020 DigitalDesignandIntegratedCircuitsInstructor:J.Wawrzynek
Lecture 5: FPGAs
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EE141
FPGAs are in widespread useFar more different designs are implemented in FPGAs than in custom chips.
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EE141 3Spring 2013 EECS150 - Lec02-SDS-FPGAs Page
CS150 Project platform: Xilinx ML505-110
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EE141
EECS151 FPGA Lab Board
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EE141
FPGA: Xilinx Virtex-5 XC5VLX110TVirtex-5 enhanced die photo
A die is an unpackaged part
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EE141 6
From die to PC board ...Ball Grid
Array (BGA)
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EE141 7
FPGA Overview❑ Basic structure: two-dimensional array of logic blocks and flip-flops with
a means for the user to configure (program): 1. the interconnection between the logic blocks, 2. the function of each block.
Simplified version of FPGA internal architecture
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Why are FPGAs Interesting?❑ Technical viewpoint: ▪ For hardware/system-designers, like ASICs -
only better: “Tape-out” new design every few minutes/hours.
▪ “reconfigurability” or “reprogrammability” may offer other advantages over fixed logic?
– In-field reprogramming? Dynamic reconfiguration? Self-modifying hardware, evolvable hardware?
Of course, the relative flexibility comes at the expense of larger die area, slower circuits, and more
energy per operation.
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Why are FPGAs Interesting?❑ Staggering logic capacity
growth (10000x):
▪ FPGAs have tracked Moore’s Law better than any other programmable device.
Year Introduced Device Logic Cells “logic gate equivalents”
1985 XC2064 128 1024
2011 XC7V2000T 1,954,560 15,636,480
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EE141
Die Photos: Virtex FPGA vs. Pentium IV
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• FGPA Vertex chip looks remarkably structured – Very dense, very regular structure
• “Full-Custom” Pentium chip somewhat more random in structure – Large on-chip memories (caches) are visible
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Why are FPGAs Interesting?▪ Logic capacity now only part of the story: on-chip
RAM, high-speed I/Os, “hard” function blocks, ... ▪ Modern FPGAs are “reconfigurable systems on
a chip”Xilinx Virtex-5 LX110T
64 ALUs
148 36Kb SRAM Blocks
10GBps Serdes
Ethernet MACs
PCI express Phy
Xilinx ZYNQ - embedded ARM cores
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EE141
FPGA Internals
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Background for upcoming technical details❑ A MUX or multiplexor is a
combinational logic circuit that chooses between 2N inputs under the control of N control signals.
❑ A latch is a 1-bit memory (similar to a SRAM storage cell).
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EE141
FPGA Programmability
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• FPGA programmability allows users to: 1.define function of configurable logic
blocks (CLBs), 2.establish interconnection paths
between CLBs 3.set other options, such as clock,
reset connections, and I/O. • Most FPGAs have “SRAM based”
programmability.
• Latch-based (Xilinx, Intel/Altera, …)
+ reconfigurable
– volatile
– relatively large.
MOSFET used as a “switch”
Programmable Cross-points
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User Programmability❑ Latches store the
configuration. ❑ Configuration bitstream is
loaded under user control. ❑ “partial reconfiguration”: a
selective part of the array can be reprogrammed without disturbing the other parts.
❑ Dynamic / runtime reconfiguration: reprogramming during a computation.
❑ Most commonly the entire device is programmed when the system is booted.
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Simplified FPGA Logic Block
❑ Look up table (LUT) ▪ implements combinational logic function
❑ Register (Flip-flop) ▪ optionally stores output of LUT
Function defined by configuration bit-stream
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4-LUT Implementation❑ n-bit LUT is implemented as a
2n x 1 memory: ▪ inputs choose one of 2n
memory locations. ▪ memory locations (latches)
are loaded with values from user’s configuration bit stream.
▪ Inputs to mux control are the logic block inputs.
❑ Result is a general purpose “logic gate”. ▪ n-LUT can implement any
function of n inputs!
LUT
LUT
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LUT as general logic gate❑ An n-lut is a direct implementation of a
function truth-table. ❑ Each latch location holds the value of
the function corresponding to one input combination.
Example: 4-lut
Example: 2-input functions
A 2-lut Implements any function of 2 inputs.
How many of these are there?
How many functions of n inputs?
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FPGA Generic Design Flow
• Design Entry: – Create your design files using:
• HDL (hardware description languages: Verilog, VHDL) • Design Implementation:
– Logic synthesis (from HDL) followed by, ▪ Partition, place, and route to create configuration
bit-stream file • Design verification:
– Reports from tools give estimated cost, performance, power
– Optionally use simulator to check function, – Load design onto FPGA device (cable connects PC to
development board), optional “logic scope” on FPGA • check operation at full speed in real environment.
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Example Partition, Placement, and Route❑ Example Circuit:
▪ collection of gates and flip-flops• Simplified FPGA structure:
Circuit combinational logic must be “covered” by 4-input 1-output LUTs.Flip-flops from circuit must map to FPGA flip-flops. (Best to preserve “closeness” to CL to minimize wiring.)Best placement in general attempts to minimize wiring.Vdd, GND, clock, and global resets are all “prewired”.
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Example Partition, Placement, and Route❑ Example Circuit:
▪ collection of gates and flip-flops
Two partitions. Each has single output, no more than 4 inputs, and no more than 1 flip-flop. In this case, inverter goes in both partitions. Note: the partition can be arbitrarily large as long as it has not more than 4 inputs and 1 output, and no more than 1 flip-flop.
A
A
B
B
INOUT
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Xilinx FPGAs (interconnect detail)
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EE141 24Spring 2013 EECS150 - Lec02-SDS-FPGAs Page
Colors represent different types of resources:
LogicBlock RAMDSP (ALUs)ClockingI/OSerial I/O + PCI
A routing fabric runs throughout the chip to wire everything together.
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EE141
State-of-the-Art - Xilinx FPGAs
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Virtex Ultra-scale
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Configurable Logic Blocks (CLBs)
Slices define regular connections to the switching fabric, and to slices in
CLBs above and below it on the die.
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Atoms: 5-input Look Up Tables (LUTs)
A[6:2] D000000000100010
....
101
111011111011111
001
Q
Q
Q
Q
Q
Q
(1)
(1)
(1)
(0)
(0)
(0)
....D
A[6:2]
Computes any 5-input logic function.
Timing is independent of function.
Latchesset during
configuration.
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Virtex 6-LUTs: Composition of 5-LUTsMay be used
as one 6-input LUT (D6 out) ...
Combinational logic
(post configuration)
... or as two 5-input LUTS (D6 and D5)
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EE141 29Spring 2013
The simplest view of a sliceFour 6-LUTs
Four Flip-Flops
Switching fabric may see combinational and registered
outputs.
An actual Virtex slice adds many small features to this simplified diagram. We show them one by
one ...
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EE141 30Spring 2013
Two 7-LUTs per slice ...
Extra multiplexers(F7AMUX,
F7BMUX)Extra inputs (AX and CX)
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EE141 31Spring 2013
Or one 8-LUTs per slice ...
Third multiplexer(F8MUX)
Third input (BX)
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EE141 32Spring 2013
Extra muxes to chose LUT option ...From eight 5-LUTs
... to one 8-LUT.
Combinational or registered outs.
Flip-flops unused by LUTs can be used
standalone.
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EE141 33Spring 2013
We can map ripple-carry addition
onto carry-chain block.
The carry-chain block also useful for speeding
up other adder structures and
counters.
Virtex Vertical Logic
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EE141 34Spring 2013 EECS150 - Lec02-SDS-FPGAs
Putting it all together ... a SLICEL.
The previous slides explain all SLICEL features.
About 50% of the are SLICELs.
The other slices are SLICEMs,
and have extra features.
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EE141 35Spring 2013
Recall: 5-LUT architecture ...
A[6:2] D000000000100010
....
101
111011111011111
001
Q
Q
Q
Q
Q
Q
(1)
(1)
(1)
(0)
(0)
(0)
....D
A[6:2]
32 Latches. Configured to 1 or 0.
Some parts of a logic design need many
state elements.
SLICEMs replace normal 5-LUTs with circuits that can act like 5-LUTs, but can alternatively use the
32 latches as RAM, ROM, shift registers.
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Virtex DSP48E Slice
Efficient implementation of multiply, add, bit-wise logical.
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EE141 37EECS150 - Lec02-SDS-FPGAs Page
To be continued ...
Throughout the semester, we will look at different FPGA features in-depth.
Switch fabricBlock RAMDSP48 (ALUs)ClockingI/OSerial I/O + PCI
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