Lecture 5. AT91- Memory Map, Timers, and AIC -

Prof. Taeweon SuhComputer Science Education

Korea University

ECM586 Special Topics in Embedded Systems

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Address Bus

0x0000

Program Execution in CPU

2

ARM (CPU)

R0

R1R2

R3

R14

R15

…

32 bitsRegisters

+

Memory

Data Bus

add r2, r2, r3ldr r3, [r5]ldr r2, [r4]

0x002200220x00110011

PC (R15)0x00000x0004

0x00180x0014

0x00080x00040x0000ldr r2, [r4]

ldr r3, [r5]

add r2 ,r2, r3

0x00140x00110011

0x00220022

0x0004

0x0018

0x00080x0008

0x00220022

0x00110011

0x00330033

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Memory Map

• Memory map indicates how memory space is laid out Examples:

• Where the main memory is located in the memory space • Where I/O devices are located in the memory space

Memory-mapped I/Os: To access registers in I/O devices, CPU should access a memory space allocated for the I/O devices

• Memory map depends on the size of the address bus If address bus is 32-bit wide, memory space is 4GB If address bus is 48-bit wide, memory space is 256TB

• Suppose that the address bus is 32-bit wide

3

CPU

North Bridge

South Bridg

e

Main Memor

y(DDR)

FSB (Front-Side Bus)

DMI (Direct Media I/F)

Memory Space

Byte address 0x00000000

0xFFFF_FFFF

Main memory(1GB)

BIOS ROM

Memory in Graphics card

0x3FFF_FFFF

0x7000_0000

0x7FFF_FFFF

0xE000_0000

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Memory Map in AT91

• Memory Map is mostly defined by hardware provider

• Like you need a map to find places, CPU needs “map” to access memory or hardware devices

• Depending on CPU, the size of the memory map is determined For example:

• if your CPU is 32-bit CPU, it would have 4GB (232) memory space (memory map)

• If your CPU is 64-bit CPU, it would have 16EB (264)?• Yeah, but it depends on how many physical address

lines come out of CPU..

4

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On-chip Peripheral Map in AT91

5

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AT91 Block Diagram

6

• CPU provide ISA (Instruction Set Architecture)

• ISA means instructions CPU provides

• If you are programming directly with instructions, you are doing assembly programming

• After compiling your assembly program, the linker combines objects and library files, relocates their code and data and tie up symbol references

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Linker Script Example• Open “Makefile” in lab 2

“make” utility makes your life easier Default input file for “make “is “Makefile” Type “man make” to see the detailed info in Linux or Google-search it with, for example,

“make linux”• “ld” is the GNU linker and “arm-linux-ld” is the GNU linker for ARM cross-compilation• The final binary (=executable) “timerirq” in the following case contains information

about where (which address) your code and data are located

7

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Example Linker Script

• Check out the Lab source code

8

Hello.lds

• This script locates your program (text) from address 0x0000_0000, where ROM is located

• Data section in your program is located, aligned at 8KB (8192) boundary

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Program Execution Path in H/W

9

ARM

ROM

CPU core

ALUEAX

R15

….

R1

R0

B reset (=EA00_0006)B . (=EAFF_FFFE)

msr CPSR, … (=E321_F0D2)

ldr sp, irq_stack (=E59F_D08C)

Address Bus

Data Bus

0x003F_FFFC0x003F_FFF8

0x0000_0020

…..0x0000_00040x0000_0000

32-bit

32-bit

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Timers in AT91

10

16-bit counter

(incrementing)

Register A (RA) (0x14)

Register B (RB)

(0x18)

Register C (RC)

(0x1C)

Counter Value (0x10)

?

?

?

clock

Reset1. SWTRG: TC_CCR (0x00)2. SYNC: external signal3. RC: if RC == counter value

• There are 3 counter channels in AT91 2 modes of operation: Capture mode and Waveform mode

Status Register (0x20)

Interrupt Enable

Register (0x24)

• Status Register: RA, RB, RC compare status etc

Base Address: 0xFFFE_0000

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Capture Mode in Timers (AT91)

11

16-bit counter

(incrementing)

Register A (RA) (0x14)

Register B (RB)

(0x18)Register C

(RC)(0x1C)

Counter Value (0x10)

?

clock

Status Register (0x20)

Interrupt Enable

Register (0x24)

reset

?

?

TIOA

Capture the counter value at which edge of TIOA (LDRA in TC_CMR)

Capture the counter value at which edge of TIO (LDRB in TC_CMR)

RC Compare Interrupt

WAVE = 0 in TC_CMR (0x04)

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Waveform Mode in Timers (AT91)

12

16-bit counter

(incrementing)

Register A (RA) (0x14)

Register B (RB)

(0x18)

Register C (RC)

(0x1C)

Counter Value (0x10)

?

clock

Status Register (0x20)

Interrupt Enable

Register (0x24)

reset

?

?

RA, RB, RC Compare Interrupts

WAVE = 1 in TC_CMR (0x04)

TIOA

TIOB

Waveform (PWM: Pulse

Width Modulation)

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Interrupt Controller (INTC)

• Typically, a computer system (including embedded systems) has an interrupt controller x86-based computer system (general-purpose computer

system) has 3 interrupt controllers! • Local APIC (Advanced Programmable Interrupt Controller)• I/O APIC • 8259

• Interrupt controller receives interrupt requests from I/O devices and sends a interrupt signal to CPU x86 allocates 2 input pins for interrupt: INTR, NMI ARM provides 2 input pins as well: nIRQ, nFIQ

• Interrupt controller provides registers with which programmers can Assign priority to each interrupt source Mask specific interrupt inputs

13

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SoC (System-on-a-Chip)

INTC in a System

14

ARM

External Inputs

(Keyboard)

Serial Port

(UART)

Timers

Watchdog Timer

Wireless NIC

(Network I/F Card)

…

Interrupt Controller

nIRQ

nFIQ

…

Priority Control

Interrupt Masking

…

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AIC (Advanced Interrupt Controller) in AT91

15

Source Vector Register 0 (0x080)

Source Vector Register 1 (0x084)

Source Vector Register 2 (0x088)

Source Vector Register 29 (0x0F0)

Source Vector Register 30 (0x0F8)

Source Vector Register 31 (0x0FC)

…..

SMR 0 (0x000)

SMR 1 (0x004)

SMR 2 (0x008)

SMR 29 (0x074)

SMR 30 (0x078)

SMR 31 (0x07C)

….. IRQ Vector Reg (0x100)

FIQ Vector Reg (0x104)

US0_IRQ

US1_IRQ

TC0_IRQ

TC1_IRQ

TC2_IRQ

IRQ0_IRQ

IRQ1_IRQ

IRQ2_IRQ

nIRQ

nFIQ

Interrupt Enable Reg (0x120)

End of Interrupt Reg (0x130)

Set Priority

Base Address: 0xFFFF_F000