Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

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Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier

description

The Lady and the Tiger Two doors containing either Ladies or Tigers

Transcript of Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Page 1: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Lecture 4: Load/Store Architectures

CS 2011

Fall 2014, Dr. Rozier

Page 2: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

LADIES AND TIGERS

Page 3: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

The Lady and the Tiger

• Two doors containing either Ladies or Tigers

Page 4: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

The Lady and the Tiger

• You will be shown two doors, to two rooms.– Each could contain either a lady or a tiger…– It could be that both rooms contain a lady, or that both

rooms contain a tiger!• You will need to reason carefully and logically to survive!• Each question, pick a door, or decide not to open a door.

– You score one point for picking a lady, or for refusing to pick if both doors contain tigers.

– Three points available for your homework/projects grade today– If you answer wrong, you may write a short paper describing what you

did wrong, and how to find the right answer, due next class.

Page 5: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

The Lady and the Tiger

• Form up into groups• On a sheet of paper, list the first and last

names of each student in the group, and pick a team name– Discuss your answers, and record them– Each group will then give their answers to the

class

Page 6: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

The Lady and the Tiger Q1

One of these is true…

In this room, there is a lady, and in the other room there is

a tiger.

The other is false…

In one of these rooms there is a lady, and in one of these

rooms there is a tiger.

Page 7: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

The Lady and the Tiger Q1

One of these is true… The other is false…

Page 8: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

The Lady and the Tiger Q2

Either both signs are false…

At least one of these rooms contains a lady

Or both are true…

A tiger is in the other room…

Page 9: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

The Lady and the Tiger Q2

Either both signs are false… Or both are true…

Page 10: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

The Lady and the Tiger Q3

Either both signs are false…

Either a tiger is in this room, or a lady is in the other room.

Or both are true…

An lady is in the other room.

Page 11: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

The Lady and the Tiger Q3

Either both signs are false… Or both are true…

Page 12: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

What does this have to do with CS?

Page 13: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

CS and CE

• What are the disciplines?– Computer Engineering?– Computer Science?

Page 14: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

What it isn’t

• "What would we like our children- the general public of the future—to learn about computer science in schools? We need to do away with the myth that computer science is about computers. Computer science is no more about computers than astronomy is about telescopes, biology is about microscopes or chemistry is about beakers and test tubes. Science is not about tools, it is about how we use them and what we find out when we do."

-- Ian Parberry

Page 15: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

What it isn’t

• A confusion of even longer standing came from the fact that the unprepared included the electronic engineers that were supposed to design, build, and maintain the machines. The job was actually beyond the electronic technology of the day, and, as a result, the question of how to get and keep the physical equipment more or less in working condition became in the early days the all-overriding concern. As a result, the topic became —primarily in the USA— prematurely known as "computer science" —which, actually is like referring to surgery as "knife science"— and it was firmly implanted in people's minds that computing science is about machines and their peripheral equipment.

-- Edsger Dijkstra

Page 16: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

What it really is

• Computer science is the study of the theoretical foundations of information and computation and of practical techniques for their implementation and application in computer systems. Computer scientists invent algorithmic processes that create, describe, and transform information and formulate suitable abstractions to model complex systems.

• Computer engineering is the process of analyzing, designing, and integrating the hardware and software systems needed for information processing or computation. Computer engineers are saddled with the difficult tasks of modeling, designing, and analyzing cyberphysical systems which solve interdisciplinary problems in a wide variety of domains.

Page 17: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

BASIC LOAD STORE

Page 18: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

ARMv6

• Remember!– RISC architecture– Load/Store architecture

Page 19: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

RISC Load/Store Architecture

Processor

Registers

Add Cmp

Load

Etc

Store

Memory

Page 20: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Loading and Storing

• ARM, MIPS, and other Load/Store Architectures– Do not support processing data in memory– Must first move data into registers before

processing.

• Sound inefficient?– In practice it isn’t!– Memory is slow, registers are fast!

Page 21: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Loading and Storing

• The Load/Store architecture paradigm

– LOAD data values you need from memory into registers

– Process data in registers

– STORE the results from the registers into memory

Processor

Registers

Add Cmp

Load

Etc

Store

Memory

Page 22: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Single register data transfer• STR

– store a word from a register

STR r0, [r1]Store r0 to the location pointed to by r1

LDR r0, [r1]Load the contents pointed to by r1 into r0

Page 23: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Single register data transfer• LDR

– load a word from memory into a register

LDR r0, [r1]Load the contents pointed to by r1 into r0

Page 24: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Offsets

• Our offset can be– An unsigned 12bit immediate value– A register

• Offset can be– Added (default)– Subtracted (prefix with a ‘-’)

Page 25: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Offsets

• Can be done:– Prefix: str r0, [r1, r2] Store r0 to

[r1+r2]– Prefix, increment:

str r0, [r1, r2]! Store r0 to [r1+r2]

r1 = r1 + r2– Postfix: str r0, [r1], r2 Store r0 to [r1]

r1 = r1 + r2

Page 26: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Load/Store with Offset

Prefix

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Load/Store with Offset

Postfix

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A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

Page 29: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

Let’s say r0 contains the BASE address ofthe array a[]

MEM0x0 x050x1 x020x2 x030x3 ??

REGr0 ??r1 ??r2 ??r3 ??r4 ??…r15

Page 30: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

mov r1, #0 ;Go for a[0+0]

MEM0x0 x050x1 x020x2 x030x3 ??

REGr0 x00r1 x00r2 ??r3 ??r4 ??…r15

Page 31: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

mov r1, #0 ;Go for a[0+0]mov r2, #0 ;Initialize sum to 0

MEM0x0 x050x1 x020x2 x030x3 ??

REGr0 x00r1 x00r2 x00r3 ??r4 ??…r15

Page 32: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

mov r1, #0 ;Go for a[0+0]mov r2, #0 ;Initialize sum to 0ldr r3, [r0, r1] ;r3 = a[0+0]

MEM0x0 x050x1 x020x2 x030x3 ??

REGr0 x00r1 x00r2 x00r3 x05r4 ??…r15

Page 33: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

mov r1, #0 ;Go for a[0+0]mov r2, #0 ;Initialize sum to 0ldr r3, [r0, r1] ;r3 = a[0+0]add r2, r2, r3 ;r2 = r2 + r3

MEM0x0 x050x1 x020x2 x030x3 ??

REGr0 x00r1 x00r2 x05r3 x05r4 ??…r15

Page 34: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

mov r1, #0 ;Go for a[0+0]mov r2, #0 ;Initialize sum to 0ldr r3, [r0, r1] ;r3 = a[0+0]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+1]

MEM0x0 x050x1 x020x2 x030x3 ??

REGr0 x00r1 x01r2 x05r3 x05r4 ??…r15

Page 35: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

mov r1, #0 ;Go for a[0+0]mov r2, #0 ;Initialize sum to 0ldr r3, [r0, r1] ;r3 = a[0+0]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+1]ldr r3, [r0, r1] ;r3 = a[0+1]

MEM0x0 x050x1 x020x2 x030x3 ??

REGr0 x00r1 x01r2 x05r3 x02r4 ??…r15

Page 36: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

mov r1, #0 ;Go for a[0+0]mov r2, #0 ;Initialize sum to 0ldr r3, [r0, r1] ;r3 = a[0+0]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+1]ldr r3, [r0, r1] ;r3 = a[0+1]add r2, r2, r3 ;r2 = r2 + r3

MEM0x0 x050x1 x020x2 x030x3 ??

REGr0 x00r1 x01r2 x07r3 x02r4 ??…r15

Page 37: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

mov r1, #0 ;Go for a[0+0]mov r2, #0 ;Initialize sum to 0ldr r3, [r0, r1] ;r3 = a[0+0]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+1]ldr r3, [r0, r1] ;r3 = a[0+1]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+2]

MEM0x0 x050x1 x020x2 x030x3 ??

REGr0 x00r1 x02r2 x07r3 x02r4 ??…r15

Page 38: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

mov r1, #0 ;Go for a[0+0]mov r2, #0 ;Initialize sum to 0ldr r3, [r0, r1] ;r3 = a[0+0]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+1]ldr r3, [r0, r1] ;r3 = a[0+1]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+2]ldr r3, [r0, r1] ;r3 = a[0+2]

MEM0x0 x050x1 x020x2 x030x3 ??

REGr0 x00r1 x02r2 x07r3 x03r4 ??…r15

Page 39: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

mov r1, #0 ;Go for a[0+0]mov r2, #0 ;Initialize sum to 0ldr r3, [r0, r1] ;r3 = a[0+0]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+1]ldr r3, [r0, r1] ;r3 = a[0+1]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+2]ldr r3, [r0, r1] ;r3 = a[0+2]add r2, r2, r3 ;r2 = r2 + r3

MEM0x0 x050x1 x020x2 x030x3 ??

REGr0 x00r1 x02r2 x0Ar3 x03r4 ??…r15

Page 40: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

mov r1, #0 ;Go for a[0+0]mov r2, #0 ;Initialize sum to 0ldr r3, [r0, r1] ;r3 = a[0+0]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+1]ldr r3, [r0, r1] ;r3 = a[0+1]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+2]ldr r3, [r0, r1] ;r3 = a[0+2]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Increment to a[0+3]

MEM0x0 x050x1 x020x2 x030x3 ??

REGr0 x00r1 x03r2 x0Ar3 x03r4 ??…r15

Page 41: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

A basic example

int a[4];a[3] = a[0] + a[1] + a[2]

mov r1, #0 ;Go for a[0+0]mov r2, #0 ;Initialize sum to 0ldr r3, [r0, r1] ;r3 = a[0+0]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+1]ldr r3, [r0, r1] ;r3 = a[0+1]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+2]ldr r3, [r0, r1] ;r3 = a[0+2]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Increment to a[0+3]str r2, [r0, r1] ;a[0+3] = r2

MEM0x0 x050x1 x020x2 x030x3 x0A

REGr0 x00r1 x03r2 x0Ar3 x03r4 ??…r15

Page 42: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Improving Performance!

int a[4];a[3] = a[0] + a[1] + a[2]

mov r1, #0 ;Go for a[0+0]mov r2, #1 ;Initialize sum to 0ldr r3, [r0], r1 ;r3 = a[0+0]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+1]ldr r3, [r0], r1 ;r3 = a[0+1]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Go for a[0+2]ldr r3, [r0], r1 ;r3 = a[0+2]add r2, r2, r3 ;r2 = r2 + r3add r1, r1, #1 ;Increment to a[0+3]str r2, [r0] ;a[0+3] = r2

MEM0x0 x050x1 x020x2 x030x3 x0A

REGr0 x00r1 x03r2 x0Ar3 x03r4 ??…r15

From 12 instructions to 9 instructions, a 25% reduction in instruction count!

Page 43: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Going further, Block Data Transfer

• LDM/STM– Load/Store Multiple– Allow between 1 and 16 registers to be

transferred to or from memory.

Page 44: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Going further, Block Data Transfer

• LDM/STM– Load/Store Multiple– Allow between 1 and 16 registers to be

transferred to or from memory.

Page 45: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

BASIC DATA PROCESSING

Page 46: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Architecture of ARM

Page 47: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Data Processing

• Basic data processing instructions

Destination RegisterOperand 1 Register Operand 2

Page 48: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Data Processing

• Basic data processing instructions

ADD Rd = Rn + Operand2SUB Rd = Rn – Operand2RSB Rd = Operand2 – Rn

Page 49: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Data Processing

• Basic data processing instructionsADD Rd = Rn + Operand2SUB Rd = Rn – Operand2RSB Rd = Operand2 – RnMOV Rd = Operand2MVN Rd = -Operand2

Operand2 is 12-bits long, and can be an immediate, or a register. How does the ARM know?

Page 50: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Operand2 is Versatile!

• Immediate value– An 8-bit constant

• Register– How many bits to address our registers r0 – r15?

Page 51: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Operand2 is Versatile!

• Immediate value– An 8-bit constant

• Register– How many bits to address our registers r0 – r15?

• At most 8-bits for our immediate or 4-bits for a register.

• We have 4 more unaccounted for bits…

Page 52: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

The ARM Barrel Shifter

• ARM architectures have a unique piece of hardware known as a barrel shifter.– Device moves bits in a word left or right.

• Most processors have stand alone instructions for shifting bits.

• ARM allows shifts as part of regular instructions.

• Allows for quick multiplication and division.

Page 53: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

The ARM Barrel Shifter

Page 54: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

The ARM Barrel Shifter

• Reality of the hardware– There are no shift

instructions– Barrel shifter can be

controlled WITH an instruction

– Can only be applied to operand 2 on instructions which use the ALU

Page 55: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Types of Shifting

• Logical Shifts– lsl – left– lsr – right

• Arithmetic Shifts– asr – right

• Rotates– ror – right– rrx – right with extend

Page 56: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Example

mov r0, r1, lsl #1

This would perform a logical shift left of 1 bit on r1, and then copy the result into r0.

mov r0, r1, lsl r2

This would do the same as before, but use the value of r2 for the shift amount.

Page 57: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Logical Shifts

• Logical shifting a number left or right has the effect of doubling or halving it.

• lsl– Highest order bit shifts into the carry flag– Lowest order bit is filled with 0.

• lsr– Lowest order bit shifts into the carry flag– Highest order bit is filled with 0.

LSL C b7 b6 b5 b4 b3 b2 b1 b0

Before 0 1 0 0 0 1 1 1 1

After 1 0 0 0 1 1 1 1 0

Page 58: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Arithmetic Shift

• Preserves the sign bit.

• asr– Extends the sign bit to the second most significant– Shifts the least significant into the carry flag.

LSL C b7 b6 b5 b4 b3 b2 b1 b0

Before 0 1 0 0 0 1 1 1 1

After 1 1 1 0 0 0 1 1 1

Page 59: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Arithmetic Shift

• Preserves the sign bit.

• asr– Extends the sign bit to the second most significant– Shifts the least significant into the carry flag.

Why isn’t there an Arithmetic Shift Left?

LSL C b7 b6 b5 b4 b3 b2 b1 b0

Before 0 1 0 0 0 1 1 1 1

After 1 1 1 0 0 0 1 1 1

Page 60: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Rotations

• Rotates bits from low order to high order

• ror– Moves bits from the lowest order to the highest, setting the carry bit in the process

with the last bit rotated out.

• rrx– Always and only rotates by one position. – Carry flag is dropped into the highest order bit. Lowest order bit is moved to the

carry flag

LSL C b7 b6 b5 b4 b3 b2 b1 b0

Before 0 0 0 0 0 1 1 1 1

After 1 1 0 0 0 0 1 1 1

Page 61: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Rotations

• ror

• rrx

Page 62: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

Adding a Shift or Rotate

• Shifts and rotates can be used with:– adc, add, and– bic– cmn, cmp– eor– mov, mvn– orr– rsb– sbc, sub– teq, tst

Page 63: Lecture 4: Load/Store Architectures CS 2011 Fall 2014, Dr. Rozier.

For next time

Homework 1 will post tonight.

Continue discussion of Chapter 2 on Thursday.