Lecture 3. Virtual Platform and ARM Intro.
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Transcript of Lecture 3. Virtual Platform and ARM Intro.
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Lecture 3. Virtual Platform and ARM Intro.
Prof. Taeweon SuhComputer Science &
EngineeringKorea University
COMP427 Embedded Systems
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Virtual Platform (Virtual Prototype)
• Virtual Platform (Virtual Prototype) is a software model of a hardware system Virtual Platform is very widely used for software development much before hardware is
ready Virtual Platform is used for the development of SoCs (System-on-Chips) and future
PC systems
• Don’t be confused with Virtual Machine! VM allows the sharing of the underlying physical machine resources between different
virtual machines, each running its own OS The software layer providing the virtualization is called a virtual machine monitor
(VMM) or hypervisor • x86 provides several instructions for virtualization
2Picture source: Whitepaper “Virtual Prototypes: When, Where And How To Use Them” from Synopsys
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Virtual Machine Examples
3
KVM (Kernel-based Virtual Machine)
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Virtual Platform
4
Your PC SoC or AP model for the year
2016
PC system model for the year 2016
Software models Software
running on new products
BIOS, Firmware and OS development
Validation software development
Firmware and RTOS porting to SoC
Applications on SoC
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Time-to-Market Benefit
5http://seminar2.techonline.com/~fundamentals/vp/player.html
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SoC Market Dynamics
6
SNUG: Synopsys Users Group
Source: Synopsys
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SoC Design Challenges
7Source: TLM2.0 presentation from CoWare
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Software Determines Project Schedules
8Source: Synopsys
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Advantages of Virtual Platform
9Source: Synopsys
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How is it different from simulators?
• In a broader sense, all the simulators may be viewed as virtual platform Benchmarks and testvectors are running on virtual
models (simulators)
• However, simulators tend to model only specific components rather than a whole system (platform) For example, Simplescalar doesn’t model peripheral
devices. So, it is not feasible to run BIOS, DOS, OS (Windows)
• http://www.simplescalar.com/
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How fast VP should run?
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• Performance comparisons of simulation, emulation, and virtual platform Hardware simulation
• Concurrent modeling• ~ IPS (Instruction / second)
Hardware emulation• Porting RTLs into reconfigurable
fabric - array of FPGAs (Field Programmable Gate Array)
• KIPS ~ MIPS depending on what you emulate
Virtual platform• ~MIPS • Able to run real-applications on top
of OS in reasonable time
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How to model VP?
• Depending on the level of accuracy you want to achieve, there are different levels of abstractions
• Level of abstractions Cycle accurate model (CA)
• Clock cycle-by-cycle accurate model
Programmer’s view model (PV, we use PV)• Highly abstracted mode• Register accurate model• Functionally correct
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Which Language to Use for Modeling?
• Verilog-HDL and VHDL Used to model cycle-accurate model Too slow (~IPS depending on complexity)
• C, C++ Used to model PV in general Also can be used for cycle-accurate modeling
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In this class…
• We are not going to use any hardware
• Instead, we are going to use a virtual platform (software model) of AT91 http://www.atmel.com/
• AT91 is an SoC (hardware chip) from Atmel www.atmel.com It includes ARM CPU and various peripherals such as timer and UART
• On top of the software model, we are going to run Assembly programs OS (Embedded Linux) Applications written in C on top of the Embeded Linux
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AT91x40
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Block Diagram of AT91x40
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• Let’s focus on CPU (ARM7TDMI) first and come back later to the system block diagram
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ARM (www.arm.com)
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ARM
19Source: 2008 Embedded SW Insight Conference
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ARM Partners
20Source: 2008 Embedded SW Insight Conference
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ARM (as of 2008)
21Source: 2008 Embedded SW Insight Conference
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ARM Brief
• ARM architecture was first developed in the 1980s by Acorn
• Spin off from Acron in 1990• Released ARM6 in early 1992• …• As of 2013, ARM architecture is the most widely used 32-
bit ISA in terms of quantity produced• In 2010 alone, 6.1 billion ARM-based processors shipped,
representing 95% of smartphones 35% of digital TV and set-top boxes 10% of mobile computers
22Source: Wikipedia
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ARM Processor Portfolio
23Source: 2008 Embedded SW Insight Conference
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Product Code
• T: Thumb• T2: Thumb-2 Enhancement• D: Debug• M: Multiplier• I: Embedded ICE (In-Circuit Emulation)• E: Enhanced DPS Extension • J: Jazelle
Direct execution of 8-bit Java bytecode in hardware• S: Synthesizable core• Z: Should be TrustZone?
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ARM Cortex Series
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• ARM Cortex-A family: Applications processors for feature-
rich OS and 3rd party applications
• ARM Cortex-R family: Embedded processors for real-time
signal processing, control applications
• ARM Cortex-M family: Microcontroller-oriented processors
for MCU, ASSP, and SoC applications Unp
aral
lele
d A
pplic
abili
ty
12k gates...
Cortex-M4SC300
Cortex-M3Cortex-M1
Cortex-M0
SC000
...2.5GHz
Cortex-A5x1-4
Cortex-A8Cortex-A9
x1-4
Cortex-A15x1-4
Cortex-R51-2
Cortex-R4
1-2
Cortex-R7
Source: ARM Processor Portfolio 2011
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ARMv7-A
26www.arm.com
SCU: Snoop Control Unit ACP: Accelerator Coherency Port
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ARM Processor Brief
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#pipeline stages Frequency Architecture Process
ARM6 (1992) 3 ~33MHz ARMv3 1.2μm
ARM7TDMI 3 ~70MHz ARMv4 0.13nm
ARM920T 5 ~400MHz ARMv4 90nm
ARM1136J 8 ~1Ghz ARMv6 65nm
Cortex-A9 8~11 (OoO) ~2GHz ARMv7 32nm
Cortex-A15 15~24 (OoO) ~2.5GHz ARMv7 22nm
OOO: Out Of Order
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Abstraction
• Abstraction helps us deal with complexity Hide lower-level detail
• Instruction set architecture (ISA) An abstract interface between the hardware
and the low-level software interface
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Abstraction Analogies
29
Combustion Engine in a car
Break system in a
car
Abstraction layer
Driver
Machine Details
Hardware board in a vending
machine
Machine Details
Customer
Abstraction layer
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Abstraction in Computer
30
Abstraction layer
Users
L2 Cache
Core0 Core1Hardware
implementation
Instruction Set Architecture (ISA)
Machine languageAssembly language
Abstraction layer
Operating Systems
Application programming using APIs
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A Memory Hierarchy
31
DDR3 HDD
2nd Gen. Core i7(2011)
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A Memory Hierarchy
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On-Chip Components
L2
CPU CoreSecondary
Storage(Disk)Re
g File
MainMemory(DRAM)
Speed (cycles): ½’s 1’s 10’s 100’s 10,000’s
Size (bytes): 100’s 10K’s M’s G’s T’s
Cost: highest lowest
L1I (Instr )
L1D (Data)
lower levelhigher level
L3
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Typical and Essential Instructions
• CPU provides many instructions It would be time-consuming to study all the
instructions CPU provides There are essential and common instructions
• Instruction categories Data processing instructions
• Arithmetic and Logical (Integer) Memory access instructions
• Load and Store Branch instructions
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Levels of Program Code (x86)
34
int main(){ int a, b, c; a = 3; b = 9; c = a + b; return c;}
a = 3;c7 45 f0 03 00 00 00 movl $0x3,-0x10(%ebp)b = 9;c7 45 f4 09 00 00 00 movl $0x9,-0xc(%ebp)
c = a + b;8b 55 f4 mov -0xc(%ebp),%edx8b 45 f0 mov -0x10(%ebp),%eax01 d0 add %edx,%eax89 45 f8 mov %eax,-0x8(%ebp)
C Compiler
Code with High-level Language
Machine Code
Instructions(human-
readable)
Representation in hexadecimal
(machine-readable)
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High-Level Code is Portable
35
int main(){ int a, b, c; a = 3; b = 9; c = a + b; return c;}
PowerBook G4(CPU: PowerPC)
x86-based Notebook
(CPU: Core 2 Duo)
Compile
Compile
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Levels of Program Code (ARM)
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• High-level language program (in C)
swap (int v[], int k){ int temp;temp = v[k];v[k] = v[k+1];v[k+1] = temp;}
• Assembly language program
swap: sll R2, R5, #2add R2, R4, R2ldr R12, 0(R2)ldr R10, 4(R2)str R10, 0(R2)str R12, 4(R2)b exit
• Machine (object, binary) code
000000 00000 00101 0001000010000000 000000 00100 00010 0001000000100000
. . .
C Compiler
Assembler
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CISC vs RISC
• CISC (Complex Instruction Set Computer) One assembly instruction does many (complex) job
• Example: movs in x86 Variable length instruction Example: x86 (Intel, AMD), Motorola 68k
• RISC (Reduced Instruction Set Computer) Each assembly instruction does a small (unit) job
• Example: lw, sw, add, slt in MIPS Fixed-length instruction Load/Store Architecture Example: MIPS, ARM
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ARM Architecture
• ARM is RISC (Reduced Instruction Set Computer) x86 ISA is based on CISC (Complex Instruction Set
Computer) even though x86 internally implements RISC-like microcode and pipelining
• Suitable for embedded systems Very small die size (low price) Low power consumption (longer battery life)
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ARM Registers
39
• ARM has 31 general purpose registers and 6 status registers (32-bit each)
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ARM Registers
40
• Unbanked registers: R0 ~ R7 Each of them refers to the same 32-bit
physical register in all processor modes. They are completely general-purpose
registers, with no special uses implied by the architecture
• Banked registers: R8 ~ R14 R8 ~ R12 have no dedicated special
purposes• FIQ mode has dedicated registers for fast
interrupt processing R13 and R14 are dedicated for special
purposes for each mode
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R13, R14, and R15• Some registers in ARM are used for special
purposes R15 == PC (Program Counter)
• x86 uses a terminology called IP (Instruction Pointer) R14 == LR (Link Register) R13 == SP (Stack Pointer)
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CPSR
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• Current Program Status Register (CPSR) is accessible in all modes• Contains all condition flags, interrupt disable bits, the current
processor mode
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CPSR in ARM
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CPSR bits
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CPSR bits
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• ARM: 32-bit mode• Thumb: 16-bit mode• Jazelle: Special mode for JAVA acceleration
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Interrupt
• Interrupt is an asynchronous signal from hardware indicating the need for attention or a synchronous event in software indicating the need for a change in execution. Hardware interrupt causes the processor (CPU) to save its state of
execution via a context switch, and begin execution of an interrupt handler.
Software interrupt is usually implemented as an instruction in the instruction set, which cause a context switch to an interrupt handler similar to a hardware interrupt.
• Interrupt is a commonly used technique in computer system for communication between CPU and peripheral devices
• Operating systems also extensively use interrupt (timer interrupt) for task (process, thread) scheduling
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Hardware Interrupt in ARM• IRQ (Normal interrupt request)
Informed to CPU by asserting IRQ pin Program jumps to 0x0000_0018
• FIQ (Fast interrupt request) Informed to CPU by asserting FIQ pin Has a higher priority than IRQ Program jumps to 0x0000_001C
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IRQFIQ
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Software Interrupt in ARM
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• There is an software interrupt instruction in ARM SWI instruction
• Software interrupt is commonly used by OS for system calls Example: open(), close().. etc
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Exception Vectors in ARM
49RAZ: Read As Zero
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Exception Priority in ARM
50