Lecture 24a, Slide 1EECS40, Fall 2004Prof. White Lecture #24a OUTLINE Device isolation methods...
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Transcript of Lecture 24a, Slide 1EECS40, Fall 2004Prof. White Lecture #24a OUTLINE Device isolation methods...
Lecture 24a, Slide 1EECS40, Fall 2004 Prof. White
Lecture #24a
OUTLINE
• Device isolation methods
• Electrical contacts to Si
• Mask layout conventions
• Process flow examples– Resistor
– N-channel MOSFET
– CMOS process flow
• Circuit extraction from layout
Lecture 24a, Slide 2EECS40, Fall 2004 Prof. White
Device Isolation Methods
• The substrate is biased to ensure that the pn junctions are never forward biased
p
n
Top View:
pp
p
(1) pn-junction isolation:Cross-Sectional View:
n
device area 1 device area 2
p p
depletion region
Lecture 24a, Slide 3EECS40, Fall 2004 Prof. White
SiO2
n
device area 1 device area 2
SiO2
(2) Oxide isolation:
ppSiO2
dielectric substrate (e.g. SiO2, Al2O3 )
(3) Silicon-on-Insulator substrate:
SiSi
device area 1 device area 2
Lecture 24a, Slide 4EECS40, Fall 2004 Prof. White
Electrical Contacts to Si
• In order to achieve a low-resistance (“ohmic”) contact between metal and silicon, the silicon must be heavily doped:
SiO2
Al
n-type Si
SiO2
n+
ND 1020 cm-3
Metal contact to n-type Si
SiO2
Al
p-type Si
SiO2
p+
NA 1019 cm-3
Metal contact to p-type Si
To contact the body of a MOSFET, locally heavy doping is used.
Lecture 24a, Slide 5EECS40, Fall 2004 Prof. White
Mask Layout
• Typically, multiple lithography steps are needed in order to fabricate an integrated circuit.– Each lithography step utilizes a mask with the desired
pattern for a specific layer.
• Computer-aided design (CAD) tools are used to generate the masks– The desired pattern for each layer is drawn, and can
be overlaid with the patterns for other layers, to make sure that they are properly aligned to each other
“Active” area
Gate (poly-Si)
Layout Example: MOSFET gate pattern overlaidwith “active area” pattern
Process layers:
Lecture 24a, Slide 6EECS40, Fall 2004 Prof. White
What if the physical mask looks like this?
Layout is all color, with the exception of a few holes
very inconvenient to draw and to display
MaskMost of the area of the exposure field is dark
“dark-field” mask
Pattern from another mask
Layout:
Lecture 24a, Slide 7EECS40, Fall 2004 Prof. White
Dark-Field / Light-Field Convention
A dark-field mask blocks our view of underlying layers
…but if we draw the “negative” (or “complement”) of masks that are dark-field, the CAD layout is much easier, and the overlaid layers are easier to visualize
To indicate that the CAD layout is the negative of the mask,label it “dark field”. “Clear field” indicates a “positive” mask.
Rather than this:
Draw only the “holes” on the layout, i.e. the clear areas
Lecture 24a, Slide 8EECS40, Fall 2004 Prof. White
Starting material: p-type wafer with NA = 1016 cm-3
Step 1: grow 500 nm of SiO2
Step 2: pattern oxide using the oxide mask (dark field)
Step 3: implant phosphorus and anneal to form an n-type layer with ND = 1020 cm-3 and depth 100 nm
Step 4: deposit oxide to a thickness of 500 nmStep 5: pattern deposited oxide using the contact mask (dark field)Step 6: deposit aluminum to a thickness of 1 mStep 7: pattern using the aluminum mask (clear field)
Starting material: p-type wafer with NA = 1016 cm-3
Step 1: grow 500 nm of SiO2
Step 2: pattern oxide using the oxide mask (dark field)
Step 3: implant phosphorus and anneal to form an n-type layer with ND = 1020 cm-3 and depth 100 nm
Step 4: deposit oxide to a thickness of 500 nmStep 5: pattern deposited oxide using the contact mask (dark field)
Oxide mask (dark field)
Contact mask (dark field)
Al mask (clear field)
Three-mask process:
Process Flow Example #1: Resistor
Layout:
A A
Starting material: p-type wafer with NA = 1016 cm-3
Step 1: grow 500 nm of SiO2
Step 2: pattern oxide using the oxide mask (dark field)
Lecture 24a, Slide 9EECS40, Fall 2004 Prof. White
p-type Si
Step 2:
Pattern oxide
Step 3: Implant & Anneal
oxide etchant
p-type Si
photoresist patterned using mask #1
phosphorus blocked by oxide
phosphorus implant:
A-A Cross-Section
SiO2
phosphorus ions
after anneal of phosphorus implant:
n+ layer
p-type Si
lateral diffusion of phosphorus under oxide during anneal
Lecture 24a, Slide 10EECS40, Fall 2004 Prof. White
n+ layer
p-type Si
Step 4: Deposit 500 nm oxide
n+ layer
p-type Si
Step 7:
Pattern metalAl
1st layer of SiO2
2nd layer of SiO2
Step 5:
Pattern oxide n+ layer
p-type Si
Open holes for metal contacts
Lecture 24a, Slide 11EECS40, Fall 2004 Prof. White
Importance of Layer-to-Layer Alignment
marginal contact
Design Rules are needed:• Interface between designer & process engineer• Guidelines for designing masks
Example of Design Rule:
If the minimum feature size is 2, then the safety margin for overlay error is .
Example: metal line to contact hole
no contact!
safety margin to allow for misalignment
Lecture 24a, Slide 12EECS40, Fall 2004 Prof. White
IC RESISTOR MASK LAYOUTS – REGISTRATION OF EACH MASK
Registration of mask patterns is critical show separate layouts to avoid ambiguity
Oxide mask (dark field)
Al mask (clear field)
Contact mask (dark field)
A A
B
B
0
1
2
“registration” shows overlay of patterns scale in m
for B-B “cut”
Registration of one mask to the next (also called “alignment” and “overlay”) is a crucial aspect of lithography
Lecture 24a, Slide 13EECS40, Fall 2004 Prof. White
Same Layout but with misregistration (misalignment)
perfect registration
A A
B
B
0
1
2
scale in m for B-B “cut”
A A
B
B
0
1
2
scale in m for B-B “cut”
Contact mask misaligned by 2m
Lets look again at cross-section A-A to understand the consequence of this misalignment. Note contact mask 2m
Lecture 24a, Slide 14EECS40, Fall 2004 Prof. White
Layout with no misregistration (misalignment)
perfect registration
A A
B
B
0
1
2
AA
STEP 7
Al
n-type layer
Lecture 24a, Slide 15EECS40, Fall 2004 Prof. White
Layout with misregistration (misalignment)
A A
B
B
0
1
2
scale in m for B-B “cut”
Contact mask misaligned by 2m
Thus we need safety margins in layout which take into account the possible tolerances in fabrication. Each process has a set of “design rules” which specify the safety margins.
This resistor is a dud … an open
circuit !!
AA
STEP 7
Al
n-type layer
Al
Lecture 24a, Slide 16EECS40, Fall 2004 Prof. White
N-channel MOSFETSchematic Cross-Sectional View
Layout (Top View) 4 lithography steps are required: 1. active area 2. gate electrode 3. contacts 4. metal interconnects
Lecture 24a, Slide 17EECS40, Fall 2004 Prof. White
1) Thermal oxidation (~10 nm “pad oxide”)
2) Silicon-nitride (Si3N4) deposition by CVD (~40nm)
3) Active-area definition (lithography & etch)
4) Boron ion implantation (“channel stop” implant)
Process Flow Example #2: nMOSFET
Lecture 24a, Slide 18EECS40, Fall 2004 Prof. White
5) Thermal oxidation to grow oxide in “field regions”
6) Si3N4 & pad oxide removal
7) Thermal oxidation (“gate oxide”)
8) Poly-Si deposition by CVD
9) Poly-Si gate-electrode patterning (litho. & etch)
10) P or As ion implantation to form n+ source and drain regions
Top view of masks
Lecture 24a, Slide 19EECS40, Fall 2004 Prof. White
11) SiO2 CVD
12) Contact definition (litho. & etch)
13) Al deposition by sputtering
14) Al patterning by litho. & etch to form interconnects
Top view of masks
Lecture 24a, Slide 20EECS40, Fall 2004 Prof. White
Challenge: Build both NMOS & PMOS transistors on a single silicon chip
• NMOSFETs need a p-type substrate
• PMOSFETs need an n-type substrate
Requires extra process steps!
CMOS Technology
oxide
p-welln-type Si
n+ n+p+p+
Lecture 24a, Slide 21EECS40, Fall 2004 Prof. White
oxiden-type wafer
*Create “p-well”
Grow thick oxide
*Remove thick oxide in transistor areas (“active region”)
Grow gate oxide
Deposit & *pattern poly-Si gate electrodes
*Dope n channel source and drains (need to protect PMOS areas)
Deposit insulating layer (oxide)
*Open contact holes
Deposit and *pattern metal interconnects
*Dope p-channel source and drains (need to protect NMOS areas)
→ At least 3 more masks, as compared to NMOS process
Conceptual CMOS Process Flow
p-welln-type Si
n+ n+p+p+
Grow thick oxide
*Remove thick oxide in transistor areas (“active region”)
Lecture 24a, Slide 22EECS40, Fall 2004 Prof. White
Cross-sectional view of wafer
SiO2
n-type Si
1. Well Formation
• Before transistor fabrication, we must perform the following process steps:
1. grow oxide layer; pattern oxide using p-well mask
2. implant phosphorus; anneal to form deep p-type regions
Additional Process Steps Required for CMOS
boron
Top view of p-well mask(dark field)
p-well
Lecture 24a, Slide 23EECS40, Fall 2004 Prof. White
We must protect the n-channel devices during the boron implantation step, and
We must protect the p-channel devices during the arsenic implantation step
“Select n-channel”
photoresist
Example: Select p-channel
2. Masking the Source/Drain Implants
“Select p-channel”
boron
oxide
p-welln-type Si
n+ n+p+p+
Lecture 24a, Slide 24EECS40, Fall 2004 Prof. White
Modify oxide mask and “select” masks:
1. Open holes in original oxide layer, for body contacts
2. Include openings in select masks, to dope these regions
Forming Body Contacts
oxide
p-welln-type Si
n+ n+p+p+ p+n+
Lecture 24a, Slide 25EECS40, Fall 2004 Prof. White
Select Masks
N-select:
oxide
p-welln-type Si
n+ n+n+
P-select:
oxide
p-welln-type Si
n+ n+p+p+ p+n+
Lecture 24a, Slide 26EECS40, Fall 2004 Prof. White
VDD
GND
Select mask(dark field & clear field)
P-well mask(dark field)
Note body contacts:• p-well to GND• n-substrate to VDD
CMOS Inverter Layout
PMOSW/L=9/2
NMOSW/L=3/2
Active(clear field)
Gate(clear field)
Contact(dark field)
Metal(clear field)
Lecture 24a, Slide 27EECS40, Fall 2004 Prof. White
Define active areas; etch Si trenchesFill trenches (deposit SiO2 then CMP)
Modern CMOS Process at a Glance
Form wells (implantation + thermal anneal)
Grow gate oxideDeposit poly-Si and pattern gate electrodes
Implant source/drain and body-contact regionsActivate dopants (thermal anneal)
Deposit insulating layer (SiO2); planarize (CMP)Open contact holes; deposit & pattern metal layer
Lecture 24a, Slide 28EECS40, Fall 2004 Prof. White
Visualizing Layouts and Cross-Sections with SIMPLer
SIMPL is a CAD tool created by Prof. Neureuther’s group
• allows IC designers to visualize device cross-sections corresponding to a fabrication process and physical layout.
A Berkeley undergraduate student, Harlan Hile, created a mini-version of SIMPL (called SIMPLer) for EECS40.
• It’s a JAVA program -> can be run on any computer, as well as on a web
server.• You can access it directly at
http://www.ocf.berkeley.edu/~hhile/SIMPLer/SIMPLer.html
Lecture 24a, Slide 29EECS40, Fall 2004 Prof. White
Lecture 24a, Slide 30EECS40, Fall 2004 Prof. White
Lecture 24a, Slide 31EECS40, Fall 2004 Prof. White
Lecture 24a, Slide 32EECS40, Fall 2004 Prof. White
Lecture 24a, Slide 33EECS40, Fall 2004 Prof. White
Lecture 24a, Slide 34EECS40, Fall 2004 Prof. White
Procedure:
1) Inspect layout and identify obvious devices: • NMOSFETs
• PMOSFETs
• wires (metal or poly-Si)
2) Identify other (often undesired) circuit components:
• resistances (e.g. associated with long wires)
• capacitances
3) Draw schematic (VDD at top, GND at bottom)
Circuit Extraction from Layouts
Lecture 24a, Slide 35EECS40, Fall 2004 Prof. White
If the active area is located within p-well region NMOS
If the active area is NOT located in p-well region PMOS
Poly-Si line crossing over an “active” region MOSFET!
Identifying a MOSFET
Field area (thick oxide)
Active area (thin oxide)
Poly-Si gate
Lecture 24a, Slide 36EECS40, Fall 2004 Prof. White
Example: Circuit Extraction from Layout