LECTURE 2: DSP Architectures
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EECS 318 CAD Computer Aided Design EECS 318 CAD Computer Aided Design LECTURE 2: DSP Architectures LECTURE 2: DSP Architectures Instructor: Francis G. Wolff [email protected] Case Western Reserve University This presentation uses powerpoint animation: please viewshow
Transcript of LECTURE 2: DSP Architectures
EECS 318 CADComputer Aided Design
EECS 318 CADComputer Aided Design
LECTURE 2: DSP Architectures
LECTURE 2: DSP Architectures
Instructor: Francis G. Wolff [email protected]
Case Western Reserve UniversityThis presentation uses powerpoint animation: please viewshow
Instruction Pipelining is the use of pipelining to allowmore than one instruction to be in some stage ofexecution at the same time.
Ferranti ATLAS (1963):•••• Pipelining reduced the average time per instruction by 375%•••• Memory could not keep up with the CPU, needed a cache.
Cache memory is a small, fast memory unit used as abuffer between a processor and primary memory
Pipelining (Designing…,M.J.Quinn, ‘87)
Most high-performance computers exhibit a great deal ofconcurrency.
However, it is not desirable to call every modern computera parallel computer.
Pipelining and parallelism are 2 methods used toachieve concurrency.
Pipelining increases concurrency by dividing a computationinto a number of steps.
Parallelism is the use of multiple resources to increaseconcurrency.
Pipelining versus Parallelism (Designing…,M.J.Quinn, ‘87)
Pipelining is Natural!
A B C D
•Laundry Example•Ann, Brian, Cathy, Daveeach have one load of clothesto wash, dry, and fold
•Washer takes 30 minutes
•Dryer takes 30 minutes
•“Folder” takes 30 minutes
•“Stasher” takes 30 minutesto put clothes into drawers
Sequential Laundry
30Task
Order
B
C
D
ATime
30 30 3030 30 3030 30 30 3030 30 30 3030
6 PM 7 8 9 10 11 12 1 2 AM
• Sequential laundry takes 8 hours for 4 loads
• If they learned pipelining, how long would laundry take?
Pipelined Laundry: Start work ASAP
Task
Order
12 2 AM6 PM 7 8 9 10 11 1
Time
B
C
D
A
3030 30 3030 30 30
Pipelined laundry takes 3.5 hours for 4 loads!
Pipelining Lessons
• Pipelining doesn’t helplatency of single task, ithelps throughput ofentire workload
• Multiple tasks operatingsimultaneously usingdifferent resources
• Potential speedup =Number pipe stages
• Pipeline rate limited byslowest pipeline stage
• Unbalanced lengths ofpipe stages reducesspeedup
• Time to “fill” pipelineand time to “drain” itreduces speedup
• Stall for Dependences
6 PM 7 8 9
Time
B
C
D
A
3030 30 3030 30 30Task
Order
RegistersRegisters
PipeliningPipelining
Cache memoryCache memory
Primary real memoryPrimary real memory
Virtual memory (Disk, swapping)Virtual memory (Disk, swapping)
Fa
ste
r
Ch
ea
pe
r
Mo
re C
apa
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Memory Hierarchy
Ideal Pipelining
IF DCD EX MEM WB
IF DCD EX MEM WB
IF DCD EX MEM WB
IF DCD EX MEM WB
IF DCD EX MEM WB
Assume instructionsare completely independent!
Maximum Speedup ≤≤≤≤ Number of stages
Speedup ≤ ≤ ≤ ≤ Time for unpipelined operation Time for longest stage
