Lecture 12 Multi-Function Timer Pulse Unit 2 (MTU2a)

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Lecture 12 Multi-Function Timer Pulse Unit 2 (MTU2a)

Transcript of Lecture 12 Multi-Function Timer Pulse Unit 2 (MTU2a)

Page 1: Lecture 12 Multi-Function Timer Pulse Unit 2 (MTU2a)

Lecture 12 Multi-Function Timer Pulse Unit 2 (MTU2a)

Page 2: Lecture 12 Multi-Function Timer Pulse Unit 2 (MTU2a)

Outline

Basic Operation Synchronous Operation PWM Modes Interrupt Sources Registers

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Overview

The RX210 Group has a on-chip multi-function timer pulse unit 2 (MTU) Each unit comprises a 16-bit timer with six channels

MTU0 to MTU5

Available operations Waveform output at compare match Input capture function (noise filter set function) Counter clear operation Simultaneous writing to multiple timer counters (TCNT) Simultaneous clearing by compare match or input capture Simultaneous register I/O by synchronous counter operation A maximum of 12-phase PWM output is available in

combination with synchronous operation 8 clocks or 7 clocks for each channel (4 clocks for MTU5) A/D converter start trigger can be generated

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Basic Operation

Each channel has TCNT and TGR TCNT performs up-counting

Also capable of free-running operation, periodic counting, and external event counting

Each TGR can be used as an input capture register or an output compare register

Counter Operation TCNT for the corresponding channel begins counting

When one of bits CST0 to CST4 in TSTR or bits CSTU5, CSTV5, and CSTW5 in MTU5.TSTR is set to 1

Free-Running Count Operation Immediately after a reset, the MTU’s TCNT counters are all

designated as free-running counters When the relevant bit in TSTR is set to 1, the TCNT counter starts

up-count operation as a free-running counter When TCNT overflows (from FFFFh to 0000h), the MTU requests an

interrupt if the corresponding TCIEV bit in TIER is 1

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Basic Operation (cont.)

After an overflow, TCNT starts counting up again from 0000h

Periodic Count Operation TCNT for the relevant channel performs periodic count

operation When compare match is selected as the TCNT clearing source TGR is designated as an output compare register for setting the

cycle Counter clearing by compare match is selected by means of bits

CCLR[2:0] in TCR After the settings have been made, TCNT starts up-count operation

when the corresponding bit in TSTR is set to 1 When the count matches the value in TGR, TCNT is cleared to 0000h If the value of the corresponding TGIE bit in TIER is 1 at this point,

the MTU requests an interrupt After a compare match, TCNT starts counting up again from 0000h

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Basic Operation (cont.)

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Basic Operation (cont.)

Free-Running Count Operation

Periodic Count Operation

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Basic Operation (cont.)

Waveform Output by Compare Match The MTU can output low or high or toggle output from the

corresponding output pin using compare match

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Basic Operation (cont.)

An example of low output and high output TCNT has been designated as a free-running counter Settings:

High is output by compare match A Low is output by compare match B

When the pin level is the same as the specified level, the pin level does not change

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Basic Operation (cont.)

An example of toggle output TCNT has been designated as a periodic counter

With counter clearing on compare match B Settings:

The output is toggled by both compare match A and compare match B

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Basic Operation (cont.)

Input Capture Function The TCNT value can be transferred to TGR on detection of the

MTIOC pin input edge The rising edge, falling edge, or both edges can be selected as the

detection edge For MTU0 and MTU1, another channel’s counter input clock or

compare match signal can be specified as the capture source

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Basic Operation (cont.)

An example of input capture operation Both rising and falling edges have been selected as the

MTIOCnA pin input capture input edge The falling edge has been selected as the MTIOCnB pin input

capture input edge Counter clearing by TGRB input capture has been made

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Synchronous Operation

The values in multiple TCNT counters can be modified simultaneously (synchronous presetting)

Multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the proper setting in TCR Synchronous operation increases the number of TGR registers

assigned to a single time base MTU0 to MTU4 can all be designated for synchronous operation MTU5 cannot be used for synchronous operation

An example of synchronous operation Synchronous operation and PWM mode 1 have been designated

for MTU0 to MTU2, MTU0 TGRB compare match has been set as the counter clearing source in

MTU0 Synchronous clearing has been set for the counter clearing source in

MTU1 and MTU2 Three-phase PWM waveforms are output from pins MTIOC0A,

MTIOC1A, and MTIOC2A

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Synchronous Operation (cont.)

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Synchronous Operation (cont.)

Synchronous presetting and synchronous clearing by MTU0.TGRB compare match are performed for the TCNT counters in MTU0 to MTU2

The data set in MTU0.TGRB is used as the PWM cycle

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Buffer Operation

Provided for MTU0, MTU3, and MTU4 Enables TGRC and TGRD to be used as buffer registers In MTU0, TGRF can also be used as a buffer register

Buffer operation differs depending on Whether TGR has been designated as an input capture register

or as a compare match register The register combinations used in buffer operation

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Buffer Operation (cont.)

When TGR is an output compare register When a compare match occurs

The value in the buffer register for the corresponding channel is transferred to the timer general register

When TGR is an input capture register When an input capture occurs

The value in TCNT is transferred to TGR and the value previously held in TGR is transferred to the buffer register

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Buffer Operation (cont.)

Buffer Operation Setting Procedure

An operation example of the output compare register PWM mode 1 has been designated for MTU0 Buffer operation has been designated for TGRA and TGRC

TCNT clearing by compare match B High output at compare match A The TTSA bit in MTU0.TBTM is set to 1

When compare match A occurs, the output changes

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Buffer Operation (cont.)

The value in buffer register TGRC is simultaneously transferred to timer general register TGRA

This operation is repeated each time compare match A occurs

An operation example of the input capture register TGRA has been designated as an input capture register Buffer operation has been designated for TGRA and TGRC

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Buffer Operation (cont.)

Counter clearing by TGRA input capture has been set for TCNT Both rising and falling edges have been selected as the MTIOCnA pin

input capture input edge When the TCNT value is stored in TGRA upon occurrence of input

capture A, the value previously stored in TGRA is simultaneously transferred to TGRC

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Buffer Operation (cont.)

The timing for transfer from buffer registers to TGR registers Can be selected in PWM mode 1 or 2 for MTU0 Or in PWM mode 1 for MTU3 and MTU4

By setting the buffer operation transfer mode registers (MTU0.TBTM, MTU3.TBTM, and MTU4.TBTM)

TBTM must be modified only while TCNT stops Either compare match (initial setting) or TCNT clearing can be

selected for the transfer timing TCNT clearing as transfer timing is one of the following cases:

When TCNT overflows (FFFFh → 0000h) When 0000h is written to TCNT during counting When TCNT is cleared to 0000h under the condition specified in the

CCLR[2:0] bits in TCR

An operation example PWM mode 1 is designated for MTU0 Buffer operation is designated for MTU0.TGRA and MTU0.TGRC

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Buffer Operation (cont.)

MTU0.TCNT clearing by compare match B High output at compare match A Low output at compare match B The TTSA bit in MTU0.TBTM is set to 1

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Cascaded Operation

16-bit counters in different two channels are used together as a 32-bit counter Works when overflow/underflow of MTU2.TCNT is selected as

the counter clock for MTU1 through the TPSC[2:0] bits in TCR Underflow occurs only when the lower 16 bits of TCNT is in phase

counting mode

For simultaneous input capture of MTU1.TCNT and MTU2.TCNT during cascaded operation Additional input capture input pins can be specified by the input

capture control register (TICCR) The input-capture condition is of edges in the signal produced by

taking the logical OR of the input level on the main input pin and the input level on the added input pin

If either is at the high, a change in the level of the other will not produce an edge for detection

The cascaded operation setting procedure

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Cascaded Operation (cont.)

Cascaded operation example 1 MTU2 overflow/underflow counting has been set for MTU1

Phase counting mode has been designated for MTU2 MTU1.TCNT is incremented by MTU2.TCNT overflow and

decremented by MTU2.TCNT underflow

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Cascaded Operation (cont.)

Cascaded operation example 2 The I2AE and I1AE bits in TICCR have been set to 1

To include the MTIOC2A and MTIOC1A pins in the MTU1.TGRA and MTU2.TGRA input capture conditions, respectively

The IOA3 to IOA0 bits in both MTU1.TIOR and MTU2.TIOR have selected the rising and falling edges for the input capture timing

The OR result of MTIOC1A and MTIOC2A input is used for the MTU1.TGRA and MTU2.TGRA input capture conditions

Cascaded Operation Example 3 The I2AE bit in TICCR has been set to 1 to include the MTIOC2A

pin in the MTU1.TGRA input capture conditions Selects occurrence of MTU0.TGRA compare match or input capture

for the input capture timing Selects the MTIOC2A rising edge for the input capture timing As MTU1.TIOR has selected occurrence of MTU0.TGRA compare

match or input capture for the input capture timing, the MTIOC2A edge is not used for MTU1.TGRA input capture condition although the I2AE bit in TICCR has been set to 1

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Cascaded Operation (cont.)

Cascaded operation example 2

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Cascaded Operation (cont.)

Cascaded operation example 3

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PWM Modes

Provided to output PWM waveforms from the external pins The output level can be selected as low, high, or toggle output

in response to a compare match of each TGR PWM waveforms in the range of 0% to 100% duty cycle can be

output according to the TGR settings By designating TGR compare match as the counter clearing source,

the PWM cycle can be specified in that register Every channel can be set to PWM mode independently

Synchronous operation is also possible

PWM Mode 1 PWM waveforms are output from the MTIOCnA and MTIOCnC

pins by pairing TGRA with TGRB and TGRC with TGRD The levels specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR

are output from the MTIOCnA and MTIOCnC pins at compare matches A and C

The levels specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and D

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PWM Modes

The initial output value is set in TGRA or TGRC If the values set in paired TGRs are identical, the output value does

not change even when a compare match occurs Up to eight phases of PWM waveforms can be output

PWM Mode 2 PWM output is generated using one TGR as the cycle register

and the others as duty registers The level specified in TIOR is output at compare matches Upon counter clearing by a synchronized register compare match,

the initial value set in TIOR is output from each pin If the values set in the cycle and duty registers are identical, the

output value does not change even when a compare match occurs In PWM mode 2, up to eight phases of PWM waveforms can be

output when using synchronous operation in combination The correspondence between PWM output pins and registers

is listed:

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PWM Modes (cont.)

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PWM Modes (cont.)

The PWM mode setting procedure

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PWM Modes (cont.)

An example of operation in PWM mode 1 TGRA compare match is set as the TCNT clearing source

Low is set as the initial output value and output value for TGRA High is set as the output value for TGRB

The value set in TGRA is used as the cycle The value set in TGRB is used as the duty

An example of operation in PWM mode 2 Synchronous operation is designated for MTU0 and MTU1 MTU1.TGRB compare match is set as the TCNT clearing source

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PWM Modes (cont.)

Low is set as the initial output and output values for TGRB High as the output value for the other TGR registers (MTU0.TGRA to

MTU0.TGRD and MTU1.TGRA) Outputting 5-phase PWM waveforms The value set in MTU1.TGRB is used as the cycle The values set in the other TGRs are used as the duty

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Phase Counting Mode

The phase difference between two external input clocks is detected TCNT is incremented or decremented accordingly This mode can be set for MTU1 and MTU2

When this mode is specified, an external clock is selected as the counter input clock TCNT operates as an up/down-counter regardless of the setting

of bits TPSC[2:0] and bits CKEG[1:0] in TCR The functions of bits CCLR[1:0] in TCR and of TIOR, TIER, and TGR

are valid Input capture/compare match and interrupt functions can be used

This can be used for two-phase encoder pulse input. If an overflow occurs, a TCIV interrupt is generated

While the TCIEV bit in the corresponding TIER is 1 If an underflow occurs, a TCIU interrupt is generated

While the TCIEU bit in the corresponding TIER is 1

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Phase Counting Mode (cont.)

The TCFD bit in TSR is the count direction flag Read the TCFD flag to check whether TCNT is counting up or down

The phase counting mode setting procedure.

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Phase Counting Mode (cont.)

Phase counting mode 1

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Phase Counting Mode (cont.)

Phase counting mode 2

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Phase Counting Mode (cont.)

Phase counting mode 3

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Phase Counting Mode (cont.)

Phase counting mode 4

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Interrupt Sources

There are three kinds of MTU interrupt source TGR input capture/compare match, TCNT overflow, and TCNT

underflow Each interrupt source has its own enable/disable bit

Allowing the generation of interrupt request signals to be enabled or disabled individually

When an interrupt source is detected, an interrupt is requested If the corresponding enable/disable bit in TIER is set to 1

Relative channel priorities can be changed by the interrupt controller The priority within a channel is fixed

Input capture/compare match interrupt If the TGIE bit in TIER is set to 1 When a TGR input capture/compare match occurs on a channel The MTU has 21 input capture/compare match interrupts

Six for MTU0, four each for MTU3 and MTU4, two each for MTU1 and MTU2, and three for MTU5

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Interrupt Sources (cont.)

Overflow interrupt If the TCIEV bit in TIER is set to 1 When a TCNT overflow occurs on a channel The MTU has five overflow interrupts

One for each channel

Underflow interrupt If the TCIEU bit in TIER is set to 1 When a TCNT underflow occurs on a channel The MTU has two underflow interrupts

One each for MTU1 and MTU2

The DTC can be activated by the TGR input capture/compare match interrupt in each channel or the overflow interrupt in MTU4

The DMAC can be activated by the TGRA input capture/compare match interrupt in each channel

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Interrupt Sources (cont.)

The A/D converter can be activated The A/D converter can be activated by the occurrence of a

TGRA input capture/compare match in each channel A compare match between MTU0.TCNT and MTU0.TGRE

activates the A/D converter A compare match between MTU0.TCNT and MTU0.TGRF

activates the A/D converter The A/D converter can be activated when an input capture or

compare match occurs between MTU0.TCNT and MTU0.TGRA or MTU0.TGRB

The A/D converter can be activated by generating A/D converter start request signal TRG4AN or TRG4BN When the MTU4.TCNT count matches the TADCORA or TADCORB

value if the UT4AE, DT4AE, UT4BE, or DT4BE bit in the A/D converter start request control register (TADCR) is set to 1

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Registers

Timer Counter (TCNT) The MTU has a total of eight TCNT counters

One each for MTU0 to MTU4 Three (MTU5.TCNTU, TCNTV, and TCNTW) for MTU5 A 16-bit readable/writable counter

Timer General Register (TGR) The MTU has a total of 21 TGR registers Six for MTU0, two each for MTU1 and MTU2 Four each for MTU3 and MTU4, and three for MTU5 TGR is a 16-bit readable/writable register Can also be designated for operation as buffer registers

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Registers (cont.)

Timer Start Registers (TSTR) TSTR (MTU0 to MTU4) and TSTR (MTU5)

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Registers (cont.)

Timer Interrupt Enable Register (TIER)

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Registers (cont.)

Timer Control Register (TCR)

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Registers (cont.)

Timer Status Register (TSR)

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Registers (cont.)

Timer I/O Control Register (TIOR)

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Registers (cont.)

Timer Synchronous Registers (TSYR)

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Registers (cont.)

Timer Mode Register (TMDR)

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Registers (cont.)

Timer Buffer Operation Transfer Mode Register (TBTM)

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Registers (cont.)

Timer Input Capture Control Register (TICCR)