Computer Architecture

Computer ArchitectureAli Saeed KhanMarch, 2015

Fundamental ConceptsComputer Architecture

CA in levels of Transformation

What is CA?The science of designing, selecting and interconnecting hardware components and designing the hardware/software interface to create computing unit that meets functional, performance, energy consumption, cost and other specific goals.

Moores LawOptional Reading:Moore, Cramming more components onto integrated circuits, Electronics Magazine, 1965.

Why Study CA?Enable better systems: make computers faster, cheaper, smaller, more reliable, Enable new applications Life-like 3D visualization 20 years ago? Virtual reality? Personalized genomics? Personalized medicine? Enable better solutions to problems Software innovation is built into trends and changes in computer architecture > 50% performance improvement per year has enabled this innovation Understand why computers work the way they do

CA todayToday is a very exciting time to study computer architecture Industry is in a large paradigm shift (to multi-core and beyond) many different potential system designs possible Many difficult problems motivating and caused by the shift Power/energy constraints -> multi-core? Complexity of design -> multi-core? Difficulties in technology scaling -> new technologies? Memory wall/gap Reliability wall/issues Programmability wall/problem Huge hunger for data and new data-intensive applications No clear, definitive answers to these problems

The Von Neumann Model/Architecture Also called stored program computer (instructions in memory). Two key properties: Stored program Instructions stored in a linear memory array Memory is unified between instructions and data Sequential instruction processing One instruction processed (fetched, executed, and completed) at a time Program counter (instruction pointer) identifies the current instr. Program counter is advanced sequentially except for control transfer instructions

Von NeumannIs this the only way????

Not the only but definitely dominant

What else?

Dataflow Model???

Dataflow ModelVon Neumann: Instruction Fetch and execute in control flow order, as specified by IP in sequence unless explicitly defined control flow

Dataflow ModelDataflow model: An instruction is fetched and executed in data flow order i.e., when its operands are ready i.e., there is no instruction pointer Instruction ordering specified by data flow dependence Each instruction specifies who should receive the result An instruction can fire whenever all operands are received Potentially many instructions can execute at the same time Inherently more parallel

Dataflow Model

Sequential (Von Neumann)Which model is more natural to you as a programmer ???

READING:Dataflow model

ISAInstruction Set ArchitectureA well-defined hardware/software interface

The CONTRACT between software/hardwareFunctional definition of operations, modes and storage locations supported by hardwarePrecise description of how to invoke, and access them

ISANo guarantees regarding,How operations are implementedWhich operations are fast and which are slowWhich operations take more power and which take less

Analogous to human language in various aspects.

ISAPerformance measurement,

(instructions/program)x(cycles/instruction)x(seconds/cycle)

CISC vs RISC (Two broad categories of ISA)(Open Discussion in next class)

What makes a good ISA?ProgrammabilityImplement abilityCompatibility

Programmability In two directions,

To HUMANSTo COMPILERS

Human ProgrammabilityWhat makes an ISA easy for a human to program in?Proximity to a high-level language (HLL)Closing the Semantic Gap

Compiler ProgrammabilityLow level primitives from which solutions can be synthesized

Find a balance between both.

ImplementabilityEvery ISA can be implemented but not every ISA can be implemented efficiently.Classic high-performance implementation techniques,Pipelining, parallel execution etc

ImplementabilityISA feature that makes implementability a challengeVariable instruction formats: Decoding effectsVariation in latencies: complicates dynamic schedulingComplex, instruction interruption

CompatibilityISA must be compatible in both directions,Forward (New programs must be able to run on old processors)Backward (New processors must support old programs)

Aspects of ISAOperand ModelMemory OnlyAccumulatorStackRegisters

Operand Model: Memory OnlyWhere (other than memory) can operands come from?And how are they specified?Example: A = B + CSeveral optionsMemory onlyadd B,C,A mem[A] = mem[B] + mem[C]

Operand Model: AccumulatorAccumulator: Implicit single element storage

Load BACC=mem[B]Add CACC=ACC + mem[C]Store Amem[A]=ACC

Operand Model: RegistersGeneral-purpose Register: multiple explicit accumulatorLoad-Store:Load B,R1Load C,R2Add R1,R2,R1Store R1,A

Which one ?Which one is the best operand model?The best model will be the one with,Lesser Code Size (fewer instructions needed for program representation)Memory traffic (number of bytes moved to and from memoryCycles per instruction

Most of the new ISAs go for load-store or a hybrid approach.

Aspects of ISAHow many Registers?Smaller and faster, put as many as u can?Directly accessed.

But not good complex structures, processors are using more and more registers

Register Windows (Self Study)

Aspects of ISAVirtual Address SizeDetermines size of addressable (usable) memoryCurrently 32-bits or 64-bits address spaces

Choosing the right size determines the lifetime of ISA

Aspects of ISAWhich is the most suitable memory addressing mode (way of specifying address)?Register-IndirectDisplacementIndex BaseMemory-indirectAuto-incrementAuto-indexingScaledPC-relative

Assignment 1Discuss each of these addressing modes, with clear examples in assembly language?Overview the pros and cons of each mode and conclude with your pick with your reason.

Submission: 16-17th March, 2015. Will be included in midterm examination.

Aspects of ISAControl Instructions? How will you test for conditions?Option I: Compare and Branch InstructionsBranch-less-than R1,10,targetOption II: Implicit condition codessubtract R2,R1,10branch-neg targetOption III: Condition registers, separate branch instructionsset-less-than R2,R1,10branch-not-equal-zero R2,target

Class DiscussionRISC vs CISC

Microarchitecture (arch)Microarchitecture (sometimes abbreviated to arch or uarch), also called computer organization, is the way a given ISA is implemented on a processor.

A given ISA may be implemented with different microarchitectures.

MicroarchitectureIn principle, a single microarchitecture could execute several different ISAs with only minor changes to the microcode.What is a microcode ???? (layer of hardware-level instructions), microprogram - microprogramming