Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.1

Lecture 1

Introduction ZynqIntroduction ZynqZynq PS vs. PLData Buses

BTE5380 - Embedded SystemsOctobre 2014

Andreas HabeggerBern University of Applied Sciences

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.2

Zynq: A Programmable SoC

Zynq-7000 family is an APSOC from XilinxComplete ARM-based processing system

application processor unit (APU)fully integrated memory controllersI/O peripherals

Tightly integrated programming logicused to extend the processing systemscalable density and performance

Flexible array of I/Owide range of external multi-standard I/Ohigh-performance integrated serial transceiversanalog-to-digital converter inputs

The slides are based on Xilinx Tutorials.

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.3

Zynq SoC Block Diagram

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.4

Processor and Hardware Logic

The Zynq-7000 SOC architecture consists of two majorsections:PS: processing system

dual ARM Cortex-A9 processors, 866MHz to 1GHzfrequencymultiple peripheralshard silicon core

PL: programmable logicshares the same FPGA series 7 programmable logiclogic cells: 28k - 444k (430k to 6.6M gates)flip-flops: 35k - 554kDSP/MAC: 80 - 2020peak DSP performance: 100 - 2622 GMACsAD converter: two 12bits

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.5

ARM Processor Architecture

ARM Cortex-A9 processor implements the ARMv7-Aarchitecture

ARMv7 is the ARM instruction set architecture ISAARMv7-A: application set that includes support for a MMUARMv7-R: real-time set that includes support for a memoryprotection unit MPUARMv7-M: microcontroller set that is the smallest set

ARMv7 ISA includes the following types of instructions (forbackward compatibility)

Thumb instructions: 16 bits, Thumb-2 instructions: 32 bitsNEON: ARMs single instruction multiple data instructions

ARM advanced microcontroller bus architecture (AMBA)protocol

AXI3: third-generation ARM interfaceAXI4: adding to existing AXI definitions (extended bursts,subsets)

Cortex is the new family of processors

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.6

ARM Cortex-A9 Processor Power

dual-core processor cluster2.5 DMIP/MHz per processorHarvard architectureself-contained 32KB L1 caches for instruction and dataexternal memory based 512KB L2 cacheautomatic cache coherencey between processor cores1 GHz operation (fastest speed grade)

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.7

Cortex-A9 Processor Micro-Architecture (1)

instruction pipelinesupports out-of-orderinstruction issue andcompletionregister renaming toenable executionspeculationnon-blockingmemory system withload-store forwardingfast loop mode ininstruction pre-fetchto low powerconsumption

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.8

Cortex-A9 Processor Micro-Architecture (2)

variable length, out-of-order, eigth-stage, super-scalarinstruction pipeline

advanced pre-fetch with parallel branch pipeline enablingearlier branch prediction and resolution

speculative executionsupports virtual renaming of ARM physical registers toremove pipeline stall due to data dependenciesincreased processor utilization and hiding of memorylatenciesincreased performance by hardware unrolling of code loopsreduced interrupt latency via speculative entry to InterruptService Routine ISR

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.9

Processor System Components

application processing unit (APU)I/O peripherals (IOP)

multiplexed I/O (MIO), extended multiplexed I/O (EMIO)

memory interfacesPS interconnectDMA

timersgeneral interrupt controller GIC

on-chip memory (OCM): RAM

debug controller: CoreSight

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.10

Processor System Interconnect (1)

programmable logicto memory

two ports to DDRone port to OCMSRAM

central interconnectenables otherinterconnects tocommunicate

peripheral masterUSB, GigE, SDIOconnects to DDRand PL via thecentralinterconnect

peripheral slaveCPU, DMA, andPL access to IOP

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.11

Processor System Interconnect (2)

processing systemmaster

two ports from theprocessingsystem toprogrammablelogicconnects the CPUblock to commonperipheralsthrough thecentralinterconnect

processing systemslave

two ports fromprogrammablelogic to theprocessingsystem

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.12

Memory Map

the Cortex-A9 processoruses 32-bit addressingall PS and PL peripheralsare memory mapped to theCortex-A9 processor coresall slave PL peripherals willbe located between:40000000 and 7FFFFFFF(connected to GP0) and80000000 and BFFFFFFF(connected to GP1)

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.13

Memory Resources

on-chip memory (OCM)RAMboot ROM

DDRx dynamic memory controllersupports LPDDR2, DDR2, DDR3

flash/static memory controllersupports SRAM, QSPI, NAMD/NOR flash

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.14

PS Boots First

CPU0 boots from OCM ROM; CPU1 goes into a sleep stateon-chip boot loader in OCM ROM (stage 0 boot)processor loads First Stage Boot Loader (FSBL) fromexternal flash memory

NORNANDQuad SPISD cardJTAG: not a memory device - used for development/debugonlyboot source selected via package bootstrapping pins

optional secure boot mode allows the loading of encryptedsoftware from the flash boot memory

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.15

Configuring the PL

the programmable logic is configured after the PS bootsperformed by application software which is accessing thehardware device configuration unit

bitstream image transfered100MHz, 32-bit PCAP stream interfacedecryption/authentication hardware option for encryptedbitstream (in secure boot mode, this option can be used forsoftware memory load)built-in DMA allows simultaneous PL configuration and OSmemory loading

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.16

Input/Output Peripherals

two GigEtwo USB

two SPI

two SD/SDIO

two CAN

two I2C

two UART

four 32-bit GPIO

static memoriesNAND,NOR/SRAM, QuadSPI

trace ports

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.17

Multiplexed I/O (MIO)

external interface to PS I/Operipheral ports

54 dedicated packagepins availablesoftware configurable

automatically added tobootloader by tools

not available for allperiphery ports

some ports can onlyuse EMIO

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.18

Extended Multiplexed I/O (EMIO)

extended interface to PSI/O peripheral ports

EMIO: peripheral port toprogrammable logicalternative to use MIOmandatory for someperipheral portsfacilitates

connection toperipheral inprogrammable logicuse of general I/O pinsto supplement MIO pinusage

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.19

PS-PL Interfaces (1)

AXI high-performance slaveports (HP0-HP3)

configurable 32-bit or 64-bitdata widthaccess to OCM and DDR onlyconversion to processingsystem clock domainAXI FIFO interface (AFI) areFIFOs (1KB) to smooth largedata transfers

AXI general-purpose ports(GP0-GP3)

two masters from PS to PLtwo slaves from PL to PS32-bit data widthconversation and sync toprocessing system clockdomain

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.20

PS-PL Interfaces (2)

one 64-bit accelerator coherence port (ACP) AXI slaveinterface to CPU memoryDMA, interrupts, event signals

processor event bus for signaling event information to theCPUPL peripheral IP interrupts to the PS general interruptcontroller (GIC)four DMA channel RDY/ACK signals

extended multiplexed I/O (EMIO) allows PS peripheralports access to PL logic and device I/O pinsclock and resets

four PS clock outputs to the PL with enable controlfour PS reset outputs to the PL

configuration and miscellaneous

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.21

PL Clocking Sources

PS clocksPS clock source from external package pinPS has three PLLs for clock generationPS has four clock ports to PL

PL has 7 series clocking resourcesPL has a different clock source domain compared to the PSthe clock to PL can be sourced from the external clockcapable pinsone of the four PS clock sources can be used for the PL

PS architecture synchronizes the clock between PL andPSPL cannot supply clock source to PSGUI interface for PL and PS clock definition

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.22

Clocking the PL

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.23

Zynq Resets

internal resetspower-on-reset (POR)watchdog resets from the three watchdogs timerssecure violation reset

PS resetsexternal resets: PS_SRST_Bwarm reset: SRSTB

PL resetsfour reset outputs from PS to PLFCLK_RESET[3:0]

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.24

AXI is Part of ARM’s AMBA Bus

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.25

Basic AXI Signaling - 5 Channels

1. read address channel2. read data channel

3. write address channel4. write data channel5. write response channel

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.26

The AXI Interface - AXI4-Lite

no burstdata width 32 or 64

Xilinx IP onlysuppports 32-bits

very small footprintbridging to AXI4handledautomatically byAXI_Interconnect

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.27

The AXI Interface - AXI4

sometimes called"Full AXI" or"memory mapped"

notARM-sanctionednames

single addressmultiple data

burst up to 256data beats

data widthparameterizable

1024 bits

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.28

The AXI Interface - AXI4-Stream

no address channel, noread and write, alwaysjust master to slave

effectively and AXI4"write data" channel

unlimited burst lengthAXI4 max 256AXI4-Lite does not burst

virtually same signalingas AXI data channels

protocol allowsmerging, packing, widthconversionsupports sparse,continuous, aligned,unaligned streams

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.29

The AXI Interface -Streaming Applications

may not have packetse.g: digital up converter:no concept of addressfree running data (in this case)AXI4-stream would optimize to a very simple interface (inthis case)

may have packetse.g: PCIe:their packets may contain different informationtypically bridge logic of some sort is needed

Introduction Zynq

Andreas Habegger

Introduction

Processing System

Processor Peripherals

AXI Bus

Conclusion

Rev. – 1.30

Conclusion

the Zynq-7000 processing platform is a system-on-chipSOC processor with embedded programmable logicthe processing system (PS) is a hard silicon dual coreconsisting of

an application processor unittwo ARM Cortex-A9 processorsNEON co-processorgeneral interrupt controllergeneral and watchdog timers

I/O peripheralsexternal memory interfaces

the programmable logic (PL) consists of 7 series deviceshigh performance AXI4 point-to-point interfacetightly coupled AXI4 ports interfacing PS and PLPS boots from a selection of external memory devicesPL is configured by and after PS bootsPS provides clocking resources to PL