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7/26/2019 Lect11 Seq
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Lecture 11:Sequential
Circuit
Desi n
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11: Sequential Circuits2CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Outline
Sequencing
Sequencing Element Design
Max and Min-Delay
Clock Skew
Time Borrowing
Two-Phase Clocking
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11: Sequential Circuits3CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Sequencing
Combinational logic
outut deends on current inuts
Sequential logic
outut deends on current and re!ious inuts "equires searating re!ious# current# $uture
Called stateor tokens
Ex% &SM# ieline
C'
clk
in out
clk clk clk
C' C'
Pieline&inite State Machine
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11: Sequential Circuits4CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Sequencing Cont.
($ tokens mo!ed through ieline at constant seed#
no sequencing elements would )e necessary
Ex% $i)er-otic ca)le
'ight ulses *tokens+ are sent down ca)le
,ext ulse sent )e$ore $irst reaches end o$ ca)le
,o need $or hardware to searate ulses
But dispersionsets min time )etween ulses
This is called wave pipeliningin circuits (n most circuits# disersion is high
Delay $ast tokens so they dont catch slow ones.
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11: Sequential Circuits5CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Sequencing Overhead
/se $li-$los to delay $ast tokens so they mo!e
through exactly one stage each cycle.
(ne!ita)ly adds some delay to the slow tokens
Makes circuit slower than 0ust the logic delay
Called sequencing o!erhead
Some eole call this clocking o!erhead
But it alies to asynchronous circuits too
(ne!ita)le side e$$ect o$ maintaining sequence
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11: Sequential Circuits6CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Sequencing Elements
Latch% 'e!el sensiti!e
a.k.a. transarent latch# D latch
Flip-flop% edge triggered
1.k.a. master-sla!e $li-$lo# D $li-$lo# D register
Timing Diagrams Transarent
2aque
Edge-trigger
D
&lo
'atch
3
clk clk
D 3
clk
D
3 *latch+
3 *$lo+
D&lo
'atch
3
clk clk
D 3
clk
D
3 *latch+
3 *$lo+
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11: Sequential Circuits7CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Latch Design
Pass Transistor 'atch
Pros
4 Tiny
4 'ow clock load
Cons
5tdro
nonrestoring
)ackdri!ing
outut noise sensiti!ity
dynamic
di$$usion inut
D 3
/sed in 6789s
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11: Sequential Circuits8CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Latch Design
Transmission gate
4 ,o 5tdro
- "equires in!erted clock D 3
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11: Sequential Circuits9CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Latch Design
(n!erting )u$$er
4 "estoring
4 ,o )ackdri!ing
4 &ixes either: 2utut noise sensiti!ity
: 2r di$$usion inut
(n!erted outut
D
;3
D 3
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11: Sequential Circuits10CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Latch Design
Tristate $eed)ack
4 Static
Backdri!ing risk
Static latches are now essential
)ecause o$ leakage
3D;
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11: Sequential Circuits11CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Latch Design
Bu$$ered inut
4 &ixes di$$usion inut
4 ,onin!erting
3D;
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11: Sequential Circuits12CMOS VLSI DesignCMOS VLSI Design4th Ed.
Latch Design
Bu$$ered outut
4 ,o )ackdri!ing
&2? delays+
- @igh clock loading
3
D;
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11: Sequential Circuits13CMOS VLSI DesignCMOS VLSI Design4th Ed.
Latch Design
Dataath latch
4 smaller
4 $aster
- un)u$$ered inut
3
D;
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11: Sequential Circuits14CMOS VLSI DesignCMOS VLSI Design4th Ed.
Flip-Flop Design
&li-$lo is )uilt as air o$ )ack-to-)ack latches
D 3
;
D
;
3
3
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11: Sequential Circuits15CMOS VLSI DesignCMOS VLSI Design4th Ed.
Enable
Ena)le% ignore clock when en A 9
Mux% increase latch D-3 delay
Clock ating% increase en setu time# skew
D 3
'atch
D 3
en
en
'atchD
3
9
6
en
'atch
D 3
en
D3
9
6
enD 3
en
&lo
&lo
&lo
Sym)ol Multilexer Design Clock ating Design
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11: Sequential Circuits16CMOS VLSI DesignCMOS VLSI Design4th Ed.
eset
&orce outut low when reset asserted
Synchronous !s. asynchronous
D
3
3
reset
D
3
D
reset
3
D
reset
reset
reset
Synchronous"eset
1synchronous"eset
Sym)ol &
lo
D 3'atch
D 3
reset reset
3
reset
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11: Sequential Circuits17CMOS VLSI DesignCMOS VLSI Design4th Ed.
Set ! eset
Set $orces outut high when ena)led
&li-$lo with asynchronous set and reset
D
3
reset
setreset
set
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11: Sequential Circuits18CMOS VLSI DesignCMOS VLSI Design4th Ed.
Sequencing "ethods
&li-$los
>-Phase 'atches
Pulsed 'atches
&li-&los
&lo
'atch
&lo
clk
6
>
clk clk
'atch
'atch
6
6
>
>-P
hase
Transarent'atches
P
ulsed
'atches
Com)inational 'ogic
Com)inational
'ogic
Com)inational
'ogic
Com)inational 'ogic'atch
'atch
Tc
Tc>
tnono!erla
tnono!erla
tw
@al$-Cycle 6 @al$-Cycle 6
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11: Sequential Circuits19CMOS VLSI DesignCMOS VLSI Design4th Ed.
#iming Diagrams
&lo
1
td
Com)inational
'ogic1
D 3
clk clk
D
3
'atch
D 3
clkclk
D
3
tcd
tsetu t
hold
tccq
tcq
tccq
tsetu
thold
tcq
tdq
tcdq
td 'ogic Pro. Delay
tcd 'ogic Cont. Delay
tcq 'atch&lo Clk-3 Pro. Delay
tccq 'atch&lo Clk-3 Cont. Delay
tdq
'atch D-3 Pro. Delay
tcdq 'atch D-3 Cont. Delay
tsetu 'atch&lo Setu Time
thold 'atch&lo @old Time
Contamination and
Proagation Delays
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11: Sequential Circuits20CMOS VLSI DesignCMOS VLSI Design4th Ed.
"a$-Dela%: Flip-Flops
&6
&>
clk
clk clk
Com)inational 'ogic
Tc
36 D>
36
D>
td
tsetutcq
( )setupsequencing overhead
pd c pcqt T t t +1 4 2 4 3
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11: Sequential Circuits21CMOS VLSI DesignCMOS VLSI Design4th Ed.
"a$ Dela%: &-'hase Latches
Tc
36'6
6
>
'>
'F
6
6
>
Com)inational
'ogic 6
Com)inational
'ogic >
3> 3FD6 D> DF
36
D>
3>
DF
D6
td6
tdq6
td>
tdq>
( )1 2sequencing overhead
2pd pd pd c pdq
t t t T t = + 1 2 3
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11: Sequential Circuits22CMOS VLSI DesignCMOS VLSI Design4th Ed.
"a$ Dela%: 'ulsed Latches
Tc
36 3>D6 D>
36
D>
D6
Com)inational 'ogic'6
'>
tw
*a+ twE tsetu
36
D>
*)+ tw
G tsetu
Tc
td
tdq
tcq
td
tsetu
( )setupsequencing overhead
a! "pd c pdq pcq pwt T t t t t + 1 4 4 4 4 2 4 4 4 43
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11: Sequential Circuits23CMOS VLSI DesignCMOS VLSI Design4th Ed.
"in-Dela%: Flip-Flops
holdcd ccqt t t C'
clk
36
D>
&6
clk
36
&
>
clk
D>
tcd
thold
tccq
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11: Sequential Circuits24CMOS VLSI DesignCMOS VLSI Design4th Ed.
"in-Dela%: &-'hase Latches
1" 2 hold nonoverlapcd cd ccqt t t t t C'
36
D>
D>
36
6
'6
>
'>
6
>
tnono!erla
tcd
thold
tccq
@old time reduced )y
nono!erla
Paradox% hold alies
twice each cycle# !s.
only once $or $los.
But a $lo is made o$
two latchesH
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11: Sequential Circuits25CMOS VLSI DesignCMOS VLSI Design4th Ed.
"in-Dela%: 'ulsed Latches
holdcd ccq pwt t t t + C'
36
D>
36
D>
t
w
'6
'>
tcd
thold
tccq
@old time increased
)y ulse width
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11: Sequential Circuits26CMOS VLSI DesignCMOS VLSI Design4th Ed.
#ime (orro)ing
(n a $lo-)ased system%
Data launches on one rising edge
Must setu )e$ore next rising edge
($ it arri!es late# system $ails
($ it arri!es early# time is wasted
&los ha!e hard edges
(n a latch-)ased system
Data can ass through latch while transarent 'ong cycle o$ logic can )orrow time into next
1s long as each loo comletes in one cycle
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11: Sequential Circuits27CMOS VLSI DesignCMOS VLSI Design4th Ed.
#ime (orro)ing E$ample
'atch
'atch
'atch
Com)inational 'ogic Com)inational'ogic
Borrowing time across
hal$-cycle )oundary
Borrowing time across
ieline stage )oundary
*a+
*)+'atch
'atch
Com)inational 'ogicCom)inational
'ogic
'oos may )orrow time internally )ut must comlete within the cycle
6
>
6
6
6
>
>
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11: Sequential Circuits28CMOS VLSI DesignCMOS VLSI Design4th Ed.
*o) "uch (orro)ing+
36'6
6
>
'>
6
>
Com)inational 'ogic 63>D6 D>
D>
Tc
Tc>
,ominal @al$-Cycle 6 Delay
t)orrow
tnono!erla
tsetu
( )#orro$ setup nonoverlap2
cT
t t t +
>-Phase 'atches
#orro$ setuppwt t t
Pulsed 'atches
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11: Sequential Circuits29CMOS VLSI DesignCMOS VLSI Design4th Ed.
Cloc, S,e)
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11: Sequential Circuits30CMOS VLSI DesignCMOS VLSI Design4th Ed.
S,e): Flip-Flops
&6
&>
clk
clk clk
Com)inational 'ogic
Tc
36 D>
36
D>
tskew
C'
36
D>
&6
clk
36
&>
clk
D>
clk
tskew
tsetu
tcq
tdq
tcd
thold
tccq
( )setup s%e$sequencing overhead
hold s%e$
pd c pcq
cd ccq
t T t t t
t t t t
+ +
+
1 4 44 2 4 4 43
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11: Sequential Circuits31CMOS VLSI DesignCMOS VLSI Design4th Ed.
S,e): Latches
36'6
6
>
'>
'F
6
6
>
Com)inational
'ogic 6
Com)inational
'ogic >
3> 3FD6 D> DF
( )
( )
sequencing overhead
1 2 hold nonoverlap s%e$
#orro$ setup nonoverlap s%e$
2
"
2
pd c pdq
cd cd ccq
c
t T t
t t t t t t
Tt t t t
+
+ +
1 2 3
>-Phase 'atches
( )
( )
setup s%e$
sequencing overhead
hold s%e$
#orro$ setup s%e$
a! "pd c pdq pcq pw
cd pw ccq
pw
t T t t t t t
t t t t t
t t t t
+ +
+ +
+
1 4 4 4 4 4 2 4 4 4 4 4 3
Pulsed 'atches
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11: Sequential Circuits32CMOS VLSI DesignCMOS VLSI Design4th Ed.
#)o-'hase Cloc,ing
($ setu times are !iolated# reduce clock seed
($ hold times are !iolated# chi $ails at any seed
(n this class# working chis are most imortant
,o tools to analyIe clock skew
1n easy way to guarantee hold times is to use >-
hase latches with )ig nono!erla times
Call these clocks 6# >*h6# h>+
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11: Sequential Circuits33CMOS VLSI DesignCMOS VLSI Design4th Ed.
Sae Flip-Flop
Past years used $li-$lo with nono!erlaing clocks
Slow nono!erla adds to setu time
But no hold times
(n industry# use a )etter timing analyIer
1dd )u$$ers to slow signals i$ hold time is at risk
D
2
;
3
3
1
2
1
11
2
2
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11: Sequential Circuits34CMOS VLSI DesignCMOS VLSI Design4th Ed.
daptive Sequencing
Designers include timing margin
5oltage
Temerature
Process !ariation
Data deendency
Tool inaccuracies
1lternati!e% run $aster and check $or near $ailures
(dea introduced as J"aIorK: (ncrease $requency until at the !erge o$ error
: Can reduce cycle time )y LF9
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11: Seq ential Circ its35CMOS VLSI DesignCMOS VLSI Design4th Ed.
Summar%
&li-&los%
5ery easy to use# suorted )y all tools
>-Phase Transarent 'atches%
'ots o$ skew tolerance and time )orrowing
Pulsed 'atches%
&ast# some skew tol N )orrow# hold time risk