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MOS Transistor

Professor Chris H. Kim

University of MinnesotaDept. of ECE

chriskim@umn.edu

www.umn.edu/~chriskim/

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MOS Transistor

DrainSource

Gate

Kuroda, IEDM panelBody

MOS Transistor

Current Equation

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Basic Operation (1)

Device is in cut -off region

Simply, two back-to-back reverse biased pn diodes.

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Basic Operation (2)

With a positi ve gate bias, electrons are pulled toward thepositi ve gate electrode

Given a large enough bias, the electrons start to invertthe surface (pn type), a conductive channel forms

Threshold voltage Vt

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Basic Operation (3)

Current flows from drain to source with a positive drainvoltage

What is current in terms of Vgs, Vds, Vbs?

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MOS Current

Ids = 0

Vgs< Vt : cut-off

Ids = eCoxW/L ((Vgs-Vt) Vds-0.5Vds2)0 < Vds < Vgs- Vt : triode (linear) mode

Ids = eCoxW/(2L) (Vgs-Vt)20 < Vgs- Vt < Vds : saturation mode

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Channel Length Modulation

dso VLL =

Pinch-off depletion layer width increases as the drainvoltage increases

Extreme case of this is punch-through

)1( dsdsatdso

odsatds VI

VL

LII

+=

=

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Simulation versus Model (NMOS)

The square-law model doesnt match well with simulations

Only fits for low Vgs, low Vds (low E-field) conditions

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Simulation versus Model (PMOS)

Not as bad as the NMOS device

Still large discrepancies at high E-field conditions

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Simulation versus Model (Ids vs. Vgs)

Saturation current does not increase quadratically

The simulated curves looks like a straight line

Main reason for discrepancy: velocity saturation

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Veloci ty Saturation

E-fields have gone up as dimensions scale

Unfortunately, carrier velocity in silicon is limited

Electron velocity saturates at a lower E-field than holes

Mobility (e=v/E) degrades at higher E-fields Simple piecewise linear model can be used

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Velocity Saturation

csat

cnn

c

e

EEforv

EEfor

EE

Ev

>=