lec4_HighLevelModel

8/10/2019 lec4_HighLevelModel

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High-Level Modeling

Lecture 4

Introduction to Verification1


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Outline

RTL-Thinking vs High-Level Thinking Structure of High-Level Code

Object-Oriented Programming

Parallel Simulation Engine Simulation Cycle



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RTL-Thinking vs High-Level Thinking

Why verification engineer must break the RTL Mindset?

Insufficient in writing testbenches that was never intended to implement

in hardware

Numerous guidelines have been imposed to obtain efficient

implementation If RTL mindset is keptverification task becomes tedious and complicated



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To avoidlatches

set all outputs ofcombinatorial blocksto default values at

the beginning of theblock

To avoidinternal buses

do not assignregistersfrom

two separate alwaysblocks

To avoid tri-state buffers

do not assign thevalue Z (VHDL) or1bz(Verilog)


RTL Guidelines: Avoiding Undesirable Hardware Structures


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All inputs must be listed in the sensitivity list of acombinatorial block

The clock and synchronous reset must be in thesensitivity list of a sequential block

Use a nonblocking assignment when assigning to a regintended to be inferred as a flip-flop

RTL Guidelines: Maintaining the Simulation Behavior


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The example above shows a simple handshaking protocol

Example:


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enum {,MAKE_REQ,

RELEASE, }state, next_state;

always_comb

begin

next_state


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Synthesizable subset puts several constraints on your coding style

With no restrictions in high-level modeling, unmaintainable, fragile

and not portable code is easy to achieve

Must have disciplinecode will need to be modified

Assume an inexperienced audience


Coding Style


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Structure of High-Level Code

Structuring code is the process of allocating portions of thefunctionality to different modules or entities

For maintainability reasons, high-level code is structured according to

functionality or need



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Structure of High-Level Code


Application of structuring principlethat enables to hide implementationdetails and decouple the usage of afunction from its implementation

A technique for minimizinginterdependencies among modules by

defining a strict externalcommunication

internal coding can be changedwithout affecting the communication,so long as the new implementationsupports the same (or upwardscompatible) external communication

Prevents a program from becoming sointerdependent that a small change

has massive ripple effects

Encapsulation


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Encapsulation

SystemVerilog tasks andfunctions can contain local variables

task send(input [7:0] data);

reg parity;

...

endtask

function [31:0] average (input [31:0] val1,

input [31:0] val2);

reg [32:0] sum;

sum = val1 + val2;

average = sum / 2;

endfunction



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Encapsulation

Local variables can be created while minimizing their scope and

potential undesirable interaction.

function bit eth_frame::compare(eth_frame to);

compare = 0;...if (this.data_len !== to.data_len) return;begin

int i;for (i = 0; i < this.data_len; i++) begin

if (this.data[i] !== to.data[i])

return;end

end

...compare = 1;endfunction: compare



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Encapsulation

The scope of variables used solely as for-loop iterators can be further

reduced by declaring them within the loop statement, ofteneliminating the need for a begin/end block

function bit eth_frame::compare(eth_frame to);

compare = 0;

...if (this.data_len !== to.data_len) return;

for (int i = 0; i < this.data_len; i++) begin

if (this.data[i] !== to.data[i])

return;

end

...

compare = 1;

endfunction: compare



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SystemVerilog has classes, modules, programs, interfaces andpackages to encapsulate any declaration used in more than one

partition.

Functions should be packaged in a class and used via a local instance

- It is preferable to use classes to encapsulate shared declarations.

- The encapsulating class will be added to the $root name spaceand thusshould be carefully named to avoid collisions.

- Classes unlike modules, must be explicitly instantiated using the new

constructor.

static variables can replace global variables


Encapsulation: Useful Subprograms


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Encapsulation: Bus-Functional Models

Stimulus applied to the design under verification via complex waveforms andprotocols can be implemented using tasks, called bus-functional models.

drives and

samples low-level

signals accordingto a predefined

protocol

tasks are available

to initiate a

transaction withthe specified data

values


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Encapsulation By default, SystemVerilog arguments are passed by value when the task is called

and when it returns. At no other time can a value flow into or out of a task via itsinterface.


class arbiter;

task request(ref output logic

bus_rq,ref input logic bus_gt);

// The new value will "flow" out

bus_rq


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Object-oriented Programming (OOP)

The next evolutionary step in language design after structured

programming

Used to identify a methodology that makes use of (and a language that

supports) classes, inheritance and polymorphism

SystemVerilog is object-oriented



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OOP: Class

A user-defined data type

A collection of variables and subprograms that create object types

Consists of:

o data members (class properties)

o tasks and functions to access the data (methods)



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OOP: Class


Data Members

consume memory

each data member is local to

each object instance can be global as well

Methods do not consume memory

are global to the class

f


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OOP: Class

A simple class declaration:

class C;

int x;

task set (int i);

x = i;endtask

function int get;

return x;

endfunction

endclass


data member

methods

d i ifi i24


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OOP: Class

An object must be created to use the class:

C c1; or C c1 = new;c1 = new;

Having created a class object, we can use the class methods to assign andlook at the data value, x:

initial

begin

c1.set(3);$display("c1.x is %d", c1.get());

end


I d i V ifi i25


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OOP: Class

Not objects:

o Modules & interfaces

are hierarchical constructs, not data structures

cannot be assigned nor passed to tasks or functions as arguments

cannot be compared or used in expressions

o Packages- cannot be instantiated



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I t d ti t V ifi ti27


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OOP: Inheritance

parent or base classoriginal class

derived class

o the new class inheriting from the base

o inherits the properties and methods of its parent or base class

o may add new properties and methods, or modify the inherited propertiesand methods

In SystemVerilog the syntax for deriving or inheriting one class from

another is this:

class Derived extends BaseClass;

// New and overridden property and method declarations

endclass




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OOP: Inheritance

Consider the example of the class Register:

class ShiftRegister extends Register;

task shiftleft; data = data > 1; endtask

endclass




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OOP: Polymorphism

polymorphism means to have many forms

classes on different branches can be treated as if they were the same

class, when viewed as a common base class

the ability to request that the same operations be performed by a

wide range of different types of things

o you can ask many different objects to perform the same action allows the redefining of methods for derived classes while enforcing a

common interface

o the 'virtual' identifier must be used when defining the base class and

method(s) within that class



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Connectivity, Time, and Concurrency

Randomization, Constrainability,

Functional coverage measurement


Parallel Simulation Engine

C

C++

Why hasnt C/C++ been used as a hardware description language

lacks three fundamental concepts for hardware designs modeling

lacks three necessary features to support the verification productivity cycle



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Features necessary to support the verification productivity cycle

Randomization

Constrainability


- increases the probability that youll take a different path in

each test case

- creates several constraints to ensure the correctness of your

random stimulus, known as valid constraints

- define the boundaries within which the randomization feature works- You can add weights so that certain sets of stimuli occur more often than

others, that is you can change the distribution function, and

- you can use the current state of the design to change these weights and

consequently the constraints for the next state

- complements the traditional code coverage by making sure all the

functionalities of the chip or system are fully verified- Coverage objects to make sure that the chip or system perform

defined coverage goals


Functional coveragemeasurement



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Fundamental concepts necessary to model hardware designs:

Connectivity

Time

Concurrency


- the ability to describe a design using simple blocks thenconnecting them together.

- implemented by directly instantiating modules and interfaces

within modules, and connecting the pins of the modules and

interfaces to wires or registers

- the ability to represent how the internal state of a design

evolves over time and to control its progression and rate

- implemented by using timing control statements such as @

and wait

- the ability to describe actions that occur at the same time,independently of each other

- implemented through separate alwaysand initialblocks




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The Problems with Concurrency:

Concurrent systems are difficult

to describe

Concurrent systems are described

using a hybrid approach

they proved much more difficult toprogram

difficulty may originate from the

mindset imposed by the early Von

Neumann architecture still used in

todays processors, or by an innate

limitation of our intellect

human beings are adept atperforming relatively complex tasks

in parallel




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Emulating Parallelism on a Sequential Processor

Concurrent threads must be executed on single processor machines

Multi-tasking operating systems are like simulators.

Simulators are time-sharing machine

Simulator do not have time slice limits

Processes simulate until they execute a timing statement




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The Simulation Cycle

Advance Time

Sampleclocking blocks

Execute module

threads

Assign zero-delay

nonblocking values

Evaluate

assertions

Execute program

threads

1

2

3

If there is nothing left to be done at the current time,

there must be either:

1. A thread waiting for a specific amount of time

2. A nonblocking value to be assigned after a non-zero

delay



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Summary

RTL mindset leads to tedious and complicated verification task.

Coding Style- Always strive for maintainability.

High-level code is structured according to functionality or need for

maintainability reasons.

Object-oriented Programming (OOP) - define data type of a data structure and

types of operations (functions) that can be applied to the data structure.

Parallel Simulation Enginerandomization, constrainability, functional

coverage measurement,connectivity, time and concurrency.

Simulation Cycle

oModule threads -model the design.

oProgram threads-model the test bench.

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