ECE2030 Introduction to Computer Engineering

Lecture 3: Switches and CMOS

Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringGeorgia TechGeorgia Tech

22

Basic Switch• A pathpath exists when the Switch Control is

closed– If (Open) OUTPUT = unknown ; Switch is open open

((OFFOFF))– Else OUTPUT = INPUT ; Switch is closedclosed

(ON)

INPUT OUTPUT

Switch Control

33

The Analogy of A Transistor

Cross SectionCross SectionAn N-Channel Metal-Oxide Semiconductor Field Effect Transistor (MOSFET)

INPUT OUTPUT

Switch Control (Gate)

44

Transistor Characteristics• Cut-offCut-off Region

– Vgs – Vt 0– No current (Ids) between drain and source

• LinearLinear (or Ohmic) Region– 0 < Vds < Vgs – Vt– Ids is a function of Vgs and Vds– Ids = β*[(Vgs-Vt)*Vds – Vds*Vds/2]

• Saturation Saturation Region– 0 < Vgs – Vt < Vds– Ids is independent of Vds– Ids = (β/2)*(Vgs-Vt)2

– β = process factor * (W/L)• VtVt : Threshold voltage, a function of

materials, doping, insulator thickness, etc.

Gate

Drain

Source

Ids Vds

Vgs

N-type MOS Transistor

55

Transistor Characteristics

66

Switches in SeriesINPUT

OUTPUT

S1

S2

Truth Table

S1 S2 PATH?OFF OFFOFF ONON OFFON ON

77

Switches in SeriesINPUT

OUTPUT

S1

S2

Truth Table (OFF/ON=0/1)

S1 S2 PATH?OFF OFF NOOFF ON NOON OFF NOON ON YES

What Function ??

88

Switches in SeriesINPUT

OUTPUT

S1

S2

Truth Table (OFF/ON=0/1)

S1 S2 PATH?0 0 0

Function = ??

99

Switches in SeriesINPUT

OUTPUT

S1

S2

Truth Table (OFF/ON=0/1)

S1 S2 PATH?0 0 00 1 0

Function = ??

1010

Switches in SeriesINPUT

OUTPUT

S1

S2

Truth Table (OFF/ON=0/1)

S1 S2 PATH?0 0 00 1 01 0 0

Function = ??

1111

Switches in SeriesINPUT

OUTPUT

S1

S2

Truth Table (OFF/ON=0/1)

S1 S2 PATH?0 0 00 1 01 0 01 1 1

Function = Logic ANDAND

1212

Switches in Parallel

INPUT

OUTPUT

S1

Truth Table

S1 S2 PATH?OFF OFF NOOFF ON YESON OFF YESON ON YES

S2

1313

Switches in Parallel

INPUT

OUTPUT

S1

Truth Table

S1 S2 PATH?0 0 0

Function =??

S2

1414

Switches in Parallel

INPUT

OUTPUT

S1

Truth Table

S1 S2 PATH?0 0 00 1 1

Function =??

S2

1515

Switches in Parallel

INPUT

OUTPUT

S1

Truth Table

S1 S2 PATH?0 0 00 1 11 0 1

Function =??

S2

1616

Switches in Parallel

INPUT

OUTPUT

S1

Truth Table

S1 S2 PATH?0 0 00 1 11 0 11 1 1

Function = Logic OROR

S2

1717

CMOS Transistor• Complementary MOS

– P-channel MOS (pMOS)– N-channel MOS (nMOS)

• pMOS– P-type source and drain

diffusions– N substrate– Mobility by holes

• nMOS– N-type source and drain

diffusions– P substrate– Mobility by electrons

Gate

Drain

Source

Gate

Source

DrainpMOS

nMOS

1818

Pass Transistor using NMOS• Assume capacitor (CL)

is initially discharged• Gate=1, Vin=1

– CL begins to conduct and charges toward 1 (Vdd) and stops at (Vdd-Vt)

– Signal is degraded

Gate=Vdd

Vin=Vdd Vout

Ground

Load Capacitor

Vgs

I

Gate=Vdd

Vin=0 Vout=Vdd

Ground

Load Capacitor

Vgs

I

• Gate=1, Vin=0– CL begins to discharge

toward 0 –

1919

Transmission Degradation using Pass Transistor

Vdd - VtVdd

Vdd (1)

Vdd - 2VtVdd

Vdd

VddVout = Vdd- N*VtStill 1??

2020

CMOS Signal Transfer Property

Gate Path0 Closed1 Open

Gate

Drain

Source

Gate

Source

Drain

Gate Path0 Open1 Closed

pMOS

nMOS

• Transmits 1 well• Transmits 0 poorly

• Transmits 0 well• Transmits 1 poorly

2121

CMOS Transmission Gate• Transmit signal from INPUT to OUTPUT

when Gate is closed

Gate (complementary of Gatecomplementary of Gate)

Source Drain

Gate

INPUT OUTPUT

Gate

pMOS nMOS OUTPUT

0 OFF OFF ZZ1 ON ON INPUT

ZZ : High-Impedance State, consider the terminal is “floating”

2222

High Impedance• When a path exists

– Impedance is low to allow ample flow of current

• When no path– Impedance is high

allowing almost no current flow between two terminals

Gate=1

DrainSource

<< 10K

>> 100M

Closed

Gate=0

DrainSourceOpen

2323

Transmission Gates

Gate = 1

0 0

Gate = 0

Transmit Logic 0

Gate = 1

1 1

Gate = 0

Transmit Logic 1

2424

Transmission Gate Symbol

Gate

Gate

INPUT OUTPUT

Gate

Gate

INPUT OUTPUT