Lec17-mem

8/3/2019 Lec17-mem

1/37

ECE2030Introduction to Computer Engineering

Lecture 17: Memory and ProgrammableLogic

Prof. Hsien-Hsin Sean Lee

School of Electrical and Computer Engineering

Georgia Tech

8/3/2019 Lec17-mem

2/37

2

Memory

Random Access Memory (RAM) Contrary to Serial Access Memory (e.g. Tape) Static Random Access Memory (SRAM)

Data stored so long as Vdd is applied 6-transistors per cell

Faster Differential

Dynamic Random Access Memory (DRAM) Require periodic refresh Smaller (can be implemented with 1 or 3 transistor)

Slower Single-Ended

Can be read and written Typically, addressable at byte granularity

Read-Only Memory (ROM)

8/3/2019 Lec17-mem

3/37

3

Block Diagram of Memory

Example: 2MB memory, byte-addressable

N = 8 (because of byte-addressability)

K = 21 (1 word = 8-bit)

2k

wordsN-bit per word

Memory Unit

N-bit Data Input

(for Write)

N-bit Data Output

(for Read)

K-bit addresslines

Read/WriteChip Enable

N

N

K

8/3/2019 Lec17-mem

4/37

4

Static Random Access Memory (SRAM)

Typically each bit is implemented with 6 transistors (6T SRAM Cell)

During read, the bitline and its inverse are precharged to Vdd (1) beforeset WL=1

During write, put the value on Bitline and its inverse on Bitline_bar beforeset WL=1

BitLineBitLine

Wordline (WL)

8/3/2019 Lec17-mem

5/37

5

Dynamic Random Access Memory (DRAM)

1-transistor DRAM cell

During a write, put value on bitline and then set WL=1

During a read, precharge bitline to Vdd (1) before assert WL to 1 Storage decays, thus requires periodic refreshing (read-sense-write)

Bitline

Wordline (WL)

8/3/2019 Lec17-mem

6/37

6

Memory Description

Capacity of a memory is described as

# addresses x Word size

Examples:

Memory # of addr # of data lines # of addr lines # of total bytes

1M x 8 1,048,576 8 20 1 MB

2M x 4 2,097,152 4 21 1 MB

1K x 4 1024 4 10 512 B

4M x 32 4,194,304 32 22 16 MB

16K x 64 16,384 64 14 128 KB

8/3/2019 Lec17-mem

7/377

How to Address Memory

1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit




0

1

2

3

D7 D6 D5 D4 D3 D2 D1 D0

4x8 Memory

2-to-4

Decoder

A0

A1

CS

ChipSelect

8/3/2019 Lec17-mem

8/378

How to Address Memory





0

1

2

3

D7 D6 D5 D4 D3 D2 D1 D0

4x8 Memory

2-to-4

Decoder

A0=1

A1=0

Access address = 0x1

CS

ChipSelect=1

8/3/2019 Lec17-mem

9/379

Use 2 Decoders





0

1

2

3

8x4 Memory2-to-4

Decoder

RowDecoder

A1

A2

1-to-2 Decoder Column Decoder

D0D1D2D3

Tristate

Buffer(read)

0 1

A0

CS

ChipSelect CS

8/3/2019 Lec17-mem

10/3710

Tristate Buffer

Similar to Transmission Gate

Could amplify signal (in

contrast to a TG)

Typically used for signaltraveling, e.g. bus

Input Output

En

Input Output

En

Output

En

EnInput

Vdd

CMOS circuit

8/3/2019 Lec17-mem

11/3711

Bi-directional Bus using Tri-state Buffer

Direction(control data flow for read/write)

A

B

Input/Output

8/3/2019 Lec17-mem

12/3712

Read/Write Memory





0

1

2

3

8x4 Memory

2-to-4Row

Decoder

A1

A2

1-to-2 Column Decoder

D0D1D2D3

0 1

A0

CS

ChipSelect = 0

CS

Rd/Wr = 0

8/3/2019 Lec17-mem

13/3713

Read/Write Memory





0

1

2

3

8x4 Memory

2-to-4Row

Decoder

A1

A2

1-to-2 Column Decoder

D0D1D2D3

0 1

A0

CS

ChipSelect = 1

CS

Rd/Wr = 1

8/3/2019 Lec17-mem

14/3714

Building Memory in Hierarchy Design a 1Mx8 using 1Mx4 memory chips

D3

D2

D1

D0

A19A18A17

A0

1Mx4

R/WCS

D7

D6

D5

D4

A19A18

1Mx4

R/WCS

A17

A0CS

8/3/2019 Lec17-mem

15/3715

Building Memory in Hierarchy Design a 2Mx4 using 1Mx4 memory chips

A19A18

A17

A0

1Mx4

R/WCS

A19A18A17

A0

1Mx4

R/WCS

A20 1-to-2Decoder

CS

1

0

D3

D2

D1

D0

Note that 1-to-2decoder is the wireitself (or usean inverter)

8/3/2019 Lec17-mem

16/3716

Building Memory in Hierarchy

Design a 2Mx8 using 1Mx4 memory chipsA19A18A17

A0

1Mx4

CS R/W

A19

A18A17

A0

1Mx4

CS R/W

A19A18A17

A0

1Mx4

CS R/W

A19A18A17

A0

1Mx4

CS R/W

D7

D6

D5

D4

D3

D2

D1

D0

A19A18A17

A0

A20 1-to-2Decoder

CS

1

0

8/3/2019 Lec17-mem

17/3717

Memory Model 32-bit address space can address up to 4GB (232)

different memory locations

Flat Memory Model

0x0A

0xB6

0x41

0xFC

LowerMemoryAddress

0x00000000

HigherMemoryAddress

0x00000001

0x00000002

0x00000003

0xFFFFFFFF 0x0D

8/3/2019 Lec17-mem

18/3718

Endianness [Danny Cohen 91]

Byte ordering

How a multiple byte data wordstored in memory

Endianness (from Gullivers Travels) Big Endian

Most significant byte of a multi-byte word is stored at the lowestmemory address

e.g. Sun Sparc, PowerPC

Little Endian Least significant byte of a multi-byte word is stored at the lowest

memory address e.g. Intel x86

Some embedded & DSP processors would supportboth for interoperability

8/3/2019 Lec17-mem

19/3719

Endianness Examples Store 0x87654321 at address 0x0000, byte-addressable

0x87

0x65

0x43

0x21

LowerMemoryAddress

HigherMemoryAddress

0x0000

0x0001

0x0002

0x0003

BIG ENDIAN

0x21

0x43

0x65

0x87

LowerMemoryAddress

HigherMemoryAddress

0x0000

0x0001

0x0002

0x0003

LITTLEENDIAN

8/3/2019 Lec17-mem

20/3720

Memory Allocation (Little Endian)

.data

.globl declaredeclare:

.align 0

.word 511

.byte 14

.align 2

.byte 14

.word 0x0B1E8143

.align 2

.ascii GAece

.half 10

.word 0x2B1E8145

.space 1

.byte 52

.align 1

.byte 16

.space 2

.byte 67

0xFF

0x01

0x00

0x00

0x0E

------

------

0

1

2

3

4

5

6

------

0x0E

0x430x81

0x1E

0x0B

------

7

8

9

a

b

c

d

------

------

0x41

e

f

10

11

0x47

0x63

12

13

0x65

0x0A

14

15

0x65

0x8117

180x45

0x2B

19

1a

0x1E

0x0016

1b

------

1c

1d

0x34

1f

20

21 0x43

0x101e

.align N: Align next datumon a 2n byte boundary

.align 0: turn off automaticalignment for .half, .word,.float, and .double till thenext .data directive

.word: 4 bytes

.half: 2 bytes

.byte: 1 byte

.space: 1-byte space

.ascii: ASCII code (American

Standard Code forInformation Interchange)

8/3/2019 Lec17-mem

21/37

21

Read Only Memory (ROM)

Permanent binary information is stored

Non-volatile memory

Power off does not erase information stored

2kwordsN-bit per work

ROMN-bit Data Output

K-bit address

linesNK

8/3/2019 Lec17-mem

22/37

22

32x8 ROM

32x8 ROM85

0

1

2

3

28

29

30

31

D7 D6 D5 D4 D3 D2 D1 D0

A4

A3

A2

A1

A0

5-to-32

Decoder

Eachrepresents32 wires

Fuse can beimplemented asa diode or a

pass transistor

8/3/2019 Lec17-mem

23/37

23

Programming the 32x8 ROMA4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

0 0 0 0 0 1 1 0 0 0 1 0 1

0 0 0 0 1 1 0 0 0 1 0 1 1

0 0 0 1 0 1 0 1 1 0 0 0 0

1 1 1 0 1 0 0 0 1 0 0 0 0

1 1 1 1 0 0 1 0 1 0 1 1 0

1 1 1 1 1 1 1 1 0 0 0 0 1

012

293031

D7 D6 D5 D4 D3 D2 D1 D0

A4

A3

A2

A1

A0

5-to-32

Decoder

8/3/2019 Lec17-mem

24/37

24

Example: Lookup Table Design a square lookup table for F(X) = X2 using ROM

X F(X)=X2

0 0

1 1

2 4

3 9

4 16

5 25

6 36

7 49

X F(X)=X2

000 000000

001 000001

010 000100

011 001001

100 010000

101 011001

110 100100

111 110001

8/3/2019 Lec17-mem

25/37

25

Square Lookup Table using ROM

X F(X)=X2

000 000000

001 000001

010 000100011 001001

100 010000

101 011001

110 100100

111 110001

0

1

2

3

F5 F4 F3 F2 F1 F0

X2

X1

X0

3-to-8

Decoder 4

5

6

7

8/3/2019 Lec17-mem

26/37

26


X F(X)=X2

000 000000

001 000001

010 000100011 001001

100 010000

101 011001

110 100100

111 110001

= X0Not Used

0

1

2

3

F5 F4 F3 F2 F1 F0

X2

X1

X0

3-to-8

Decoder 4

5

6

7

8/3/2019 Lec17-mem

27/37

27


X F(X)=X2

000 000000

001 000001

010 000100

011 001001

100 010000

101 011001

110 100100

111 110001

0

1

2

3

F5 F4 F3 F2 F0

X2

X1

X0

3-to-8

Decoder 4

5

6

7

F1

8/3/2019 Lec17-mem

28/37

28

Classifying Three Basic PLDs

Fixed AND plane(decoder)

ProgrammableOR plane

Programmable

Connections

(Programmable) Read-Only Memory (ROM)

INPUT OUTPUT

ProgrammableOR plane

ProgrammableConnections

Programmable Logic Array (PLA)

ProgrammableAND plane

INPUT OUTPUT

ProgrammableAND plane

FixedOR plane

Programmable Array Logic (PAL) DevicesPAL: trademark of AMD, use PAL as an adjective orexpect to receive a letter from AMDs lawyers

INPUTOUTPUT

F/F

8/3/2019 Lec17-mem

29/37

29

Programmable Logic Array (PLA)

C

B

A

C C B B A A

F2

ProgrammableAND Plane

ProgrammableOR Plane

8/3/2019 Lec17-mem

30/37

30

Example using PLA

m(0,5,6,7C)B,F2(A,m(0,1,2,4)C)B,F1(A,

CBAACABF2

BCACABF1

CBCABAF1

8/3/2019 Lec17-mem

31/37

31

Example using PLA

C

B

A

C C B B A A

CBAACABF2

BCACABF1

AB

AC

BC

A B C

F2

F1

8/3/2019 Lec17-mem

32/37

32

PAL Device

A

B

IO1

IO2

IO1 IO1B BA A IO1 IO2

ProgrammableAND Plane

FixedOR Plane

8/3/2019 Lec17-mem

33/37

33

PAL Device Design Example

A

B

IO1

IO2

IO1 IO1B BA A

DCBADCADCBACABIO2

DCBACABIO1

D DC C

Not programmed

8/3/2019 Lec17-mem

34/37

34

CPLD and FPGA [Brown&Rose 96]

Complex Programmable Logic Device (CPLD) Multiple PLDs (e.g. PALs, PLAs) with programmableinterconnection structure

Pioneered by Altera

Field-Programmable Gate Array (FPGA)

High logic capacity with large distributed interconnectionstructure

Logic capacity number of 2-input NAND gates

Offers more narrow logic resources CPLD offers logic resources w/ a wide number of inputs (AND

planes) Offer a higher ratio of Flip-flops to logic resources than

CPLD

HCPLD (High Capacity PLD) is often used to referto both CPLD and FPGA

8/3/2019 Lec17-mem

35/37

35

CPLD structure

PLD PLD PLD PLD

PLD PLD PLD PLD

Logic block

Interconnects

I/O block

8/3/2019 Lec17-mem

36/37

36

FPGA Structure

Logic block

I/O block

Interconnects

8/3/2019 Lec17-mem

37/37

FPGA Programmability

Floating gate transistor

Used in EPROM and EEPROM

SRAM-controlled switch Control

Pass transistors

Multiplexers (to determine how to route inputs)

Antifuse

Similar to fuse

Originally an Open-Circuit

One-Time Programmable (OTP)

Lec17-mem

Documents

Transcript of Lec17-mem