Lec08
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Transcript of Lec08
![Page 1: Lec08](https://reader033.fdocuments.in/reader033/viewer/2022042818/55ac58a91a28ab3a348b4633/html5/thumbnails/1.jpg)
Dr A SahuDept of Computer Science &
Engineering IIT Guwahati
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• Peripheral communications
• DAC– Properties
– Generic Model
– Interfacing
• ADC– Properties
– Generic Model
– Interfacing
• Display
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• Peripherals : HD monitor, 5.1 speaker
• Interfaces : Intermediate Hardware
– Nvidia GPU card, Creative Sound Blaster card
• Interfaces : Intermediate Software/Program
– Nvidia GPU driver , Sound Blaster Driver software
Processor RAM
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• Read Instruction from memory
• Execute instruction
• Read/Write data to memory
• Some time send result to output device
– LEDs, Monitor, Printer
• Interfacing a peripheral
– Why: To enable MPU to communicate with I/O
– Designing logic circuit H/W for a I/O
– Writing instruction (S/W)
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• Transmission Controller:– MPU control, Device Control (DMA)
• Type of IO mapping– Peripheral (IN/Out), Memory mapped IO (LD/ST,MV)
• Format of communication– Synchronous (T & R sync with clock), Asynchronous
• Mode of Data Transfer – Parallel, Serial (UART)
• Condition for data transfer – Uncond., Polling, Interrupt, Ready signal, Handshake
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• Used for play sound in speaker
• Used by AC97 (Audio codec)
• MP3 Sound store digital format in HDD
• Slow as compared to processor/MPU
• Parameters• Resolution (8 bit/16 bit)
• Settling time (1micro sec)
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• FullScaleOutput=(FullScaleValue – 1LSBValue)
• 1MSB Value=1/2 * FSV
Digital to
Analog Converter
D0
D1
D2
Analog Output
Vo
Digital Inputs
An
alo
g o
utp
ut
000 001 011010 100 101 111110
LSB
FS
0
1
23
4
5
6
7
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4K2.5K
5K
10K
20K
D3=8
D2=4
D1=2
D0=1
Vout
• Vo= Vref/R * ( A1/2+ A2/4+…An/2n)
• Vo is proportional to values of Data Bits Value
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• Resistive Ladder Network • Require two type Resistor
• But small value
– 5K and 10K
2R||2R=R
R+R=2R
R
2R
2R
2R
2R
R
Vout
R
R
+
Resistor
REGISTER
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• Glitches cause waveform distortion, spurs and elevated noise floors
• High-speed DAC output is often followed by a de-glitchingSHA (Hold Buffer)
• Cause: Signal and clock skew in circuits
• Especially severe at MSB transition where all bits are switching –
0111…111 →
1000…000Time
Vo
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• Resolution
• Reference Voltages
• Settling Time
• Linearity
• Speed
• Errors
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• Amount of variance in output voltage for every change of the LSB in the digital input.
• How closely can we approximate the desired output signal(Higher Res. = finer detail=smaller Voltage divisions)
• A common DAC has a 8 - 12 bit Resolution
NLSB
VV
2Resolution Ref N = Number of bits
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Better Resolution(3 bit)Poor Resolution(1 bit)
Vout
Desired Analog
signal
Approximate
output
2 V
olt
. L
evels
Digital Input0 0
1
Digital Input
Vout
Desired Analog
signal
Approximate
output
8 V
olt
. L
evels
000
001
010
011
100
101
110
111
110
101
100
011
010
001
000
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• A specified voltage used to determine how each digital input will be assigned to each voltage division.
• Types:
– Non-multiplier: internal, fixed, and defined by manufacturer
– Multiplier: external, variable, user specified
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• Settling Time: The time required for the input signal voltage to settle to the expected output voltage(within +/- VLSB).
• Any change in the input state will not be reflected in the output state immediately. There is a time lag, between the two events.
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Analog Output Voltage
Expected
Voltage
+VLSB
-VLSB
Settling timeTime
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17
Linearity(Ideal Case)
Digital Input
Perfect Agreement
Desired/Approximate Output
Anal
og O
utp
ut
Volt
age
NON-Linearity(Real World)
Anal
og O
utp
ut
Volt
age
Digital Input
Desired Output
Miss-alignment
Approximate output
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• Gain Error: Difference in slope of the ideal curve and the actual DAC output
High Gain Error: Actual slope greater than ideal
Low Gain Error: Actual slope less than ideal
Digital Input
Desired/Ideal OutputA
nalo
g O
utp
ut
Volt
age
Low Gain
High Gain
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• Rate of conversion of a single digital input to its analog equivalent
• Conversion Rate
– Depends on clock speed of input signal
– Depends on settling time of converter
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• Used when a continuous analog signal is required.
• Signal from DAC can be smoothed by a Low pass filter
0 bit
nth bit
n bit DAC011010010101010100101101010101011111100101000010101010111110011010101010101010101010111010101011110011000100101010101010001111
Digital Input
Filter
Piece-wise Continuous Output
Analog Continuous Output
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• Design an output port with Address FFH to interface 1408 DAC
• Write a program to generate a continuous RAMP waveform
Time
Output
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8085MPU
A15
A0
D0
D7
Address Bus (16bit)
Data Bus (8bit)
A7
A6
A5
A4
A3
A2
A1
A0
74LS373Latches
1408
LED7
D6
D5
D4
D3
D2
D1
D0
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MVI A, 00H ; Load Acc with first I/P
DTOA: OUT FFH ; Output to DAC
MVI B, COUNT ; Setup Reg. for Delay
DCR B
JNZ DELAY
INR A ; Next Input
JMP DTOA ; Go back to Output
Slope of RAMP can be varied by changing Delay
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• ADC are slower then DAC
• Interfaced using Status Check
Analog to Analog
Converter D0
D1
D2
Analog Input
Vi
Analog Input D
igit
al o
utp
ut
LSB
000
001
010011
100
101
110
111
0 1 2 3 4 5 6 7
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• Sampling • Fourier Transform
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• The process of reconstructing a signal from its values at discrete instants of time
– Zero order hold or One Point
– Linear or Two Point
– Band limited or Low pass Filtering
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• Suppose my range is 0-1024 and assume some value of N between 0-1024
• You have to find the value of N
– You can ask me (what about value X)
– Answer ( N>X, N<X, N==X)
– Operation with X (X++; X*2, X^2, X/2, X--)
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• What is the best Algorithm to find – Sequential ( increase X till X==N) O(N) algorithm
– Successive approximation: (Binary Search)• Say R/2 as CMP( R/2, N) === if equal stop
IF (R/2 < N) CMP (R/2+R/4,N)
ELSE CMP (R/2-R/4, N)
• If you have N persons to do the comparisons– Ask to all people and Gather the information
• Mix of Both approach – If you have M comparator
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• Counter or Tracking ADC
• Successive Approximation ADC– Most Commonly Used
• Parallel or Flash ADC– Fast Conversion
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• Block diagram
• Waveform
• Operation
– Reset and Start Counter
– DAC convert Digital output of Counter to Analog signal
– Compare Analog input and Output of DAC• Vi < VDAC
– Continue counting
• Vi = VDAC
– Stop counting
– Digital Output = Output of Counter
• Disadvantage
– Conversion time is varied• 2n Clock Period for Full Scale
input
ClockControl
Logic Counter
DACVi
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• Most Commonly used in medium to high speed Converters
• Based on approximating the input signal with binary code and then successively revising this approximation until best approximation is achieved
• SAR(Successive Approximation Register) holds the current binary value
• Block Diagram
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• Circuit waveform
• Logic Flow
• Conversion Time
– n clock for n-bit ADC
– Fixed conversion time
• Serial Output is easily generated
– Bit decision are made in serial order
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• Very High speed conversion
– Up to 100MHz for 8 bit resolution
– Video, Radar, Digital Oscilloscope
• Single Step Conversion
– 2n –1 comparator
– Precision Resistive Network
– Encoder
• Resolution is limited
– Large number of comparator in IC
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A/DConverter
Digital O/P
Vinput
Start
Ready
START RD
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A/DConverter
Digital O/P
Vinput
Start
Ready
START RD
Tri-StateBuffer
8085MPU
A15
A0
D0
D7
Address Bus (16bit)
Data Bus (8bit)
A6
A5
A4
A3IO/W
74LS
138
E1 E2 E3
A7
IO/R
o2
o1
o0
82H
81H
80H
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OUT 82H ; Start Conversion
TEST: IN 80H ;Read DR Status
RAR ; Rotate Do to carry
JC TEST ; if Do==1 conv. done
IN 81H ; Read the output
RET ; Return
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7 Seg 9 Seg 16 Seg 3x5 DotMatix 5x7 9x11
Dot Matrix Display Panel
25x80 character monitor
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DataASCII/BCD
DecoderOr
Memory
Display
Monitor/LEDs
Time to Decode Time to Display
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• Data to 7 Seg Decoder
a
b
c
d
e
f
g
Common Cathode
a
b
c
f
g
e
d
D
C
B
A
LT
RBI
BI
Decoder
5V
0
1
0
1
1
0
1
1
10
1
5
5v
5V
0
1
0
1
1
1
1
1
11
1
5
5v
RBO
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• Data to 7 Seg Decoder
a b c d e f g
D C B A
RBI RBO
a b c d e f g
D C B A
RBI RBO
a b c d e f g
D C B A
RBI RBO
a b c d e f g
D C B A
RBI RBO
a b c d e f g
D C B A
RBI RBO
5V
0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 1 1
10
Blank
0
Blank
1 1
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• R S Gaonkar, “Microprocessor Architecture”, Unit II preface, Chapter 13
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