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Implementing Registers in CMOS (cont.)

Another example: D latch (register)Uses transmission gateWhen WR asserted, write operation will take placeStack D latch structures to get n-bit register

D

WRQ Q

WR

EE 5324 -VLSI Design II - Kia Bazargan 5

WR

WR

Shift Registers: Idea

Shift registers are used for iteratively shifting dataUsed in pipelining, bit-by-bit processing, etc.

DD1

D1 D2

D2 D3

D3

D1 D2 D3 Problem?

When clock goes high, the data will traverse all


the shift registers chain in one clock cycle!Solution: use non overlapping clocks1 and 2.1 used by odd gates,2 by even gates (usexmission gates after D1, D2, D3).

Memory Architecture: the Big Picture

Address: which one of the M words to access Data: the N bits of the word are read/written

Storagecells

Word 0Word 1

Word M-2Word M-1

. . .

S0S1S

2

SM-2S

... Word 0Word 1

. . .

S0S1S2

...

D e c o d

...

A0A1

Addressdecoder

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wordselectlines

N bits

-Word M-2Word M-1

N bits

M-2SM-1

r k-1

k = log 2 (M)

Memory Access Timing: the Big Picture

Timing:Send address on the address lines,wait for the word line to become stableRead/write data on the data lines

READ

WRITE

Read Access Read Access

Read Cycle

Write Cycle

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[Prentice Hall]

DATA

Data Valid Data Written

Write Access

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Hierarchical Memory Structure

Taking the idea one step furtherShorter wires within each block Enable only one block addr decoder power savings

Blk EN

RowAddress

ColumnAddress

Block


Blk ENBlk ENAddress

Global Bus

SAmp/Drv

Global drivers/sense amplifiers

[Rab96] p. 558

Decreasing Word Line Delay

Word line delay comes into play!We used to have long busses, made 2D arrayshorter bussesBut, longer word lines!

How to decrease the delay on the word lines?Break the word line by inserting buffersPlace the decoder in the middlePolysilicon word line Polysilicon word line


[Prentice Hall]

(a) Drive the word linefrom both sides

Metal word line

(b) Use metal bypass

Metal bypass

Decreasing Word Line Delay (cont.)

Place the decoder in the middle Add buffers to outputs of decoder

d

ecode

memorycell array

memorycell array


[Hauck]

r

Address lines

k

Array-Structured Memory Architecture

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Semiconductor MemoryClassification

Non-VolatileRead-Write Memory Read-Write

Memory

Read-Only Memory

EPROM

E2PROM

FLASH

RandomAccess

Non-RandomAccess

SRAM

Mask-Programmed

Programmable (PROM)

FIFO

17

DRAMShift Register

CAM

LIFO

Read-Write Memories (RWM) Basic storage elements of semiconductor

memoryRAM

SRAM DRAM

18

: ce as ga n , , , , og ccompatible, differential

DRAM: cell has no gain , 1T, refresh, slow, DRAM process,single ended, DENSE

Memory Scaling Trend

19

High density is the primary design goal for memories Low voltage operation is essential for low power

Itoh, IBM R&D, 2003

Memory Scaling Trend

Long retention timelow Ioff

High Vt is required Fast access time

high Ion High Vgs-Vt is

required

20

scaled downaggressively for lowpower consumption

Itoh, IBM R&D, 2003

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Why SRAMs are Important

0.18 mCoreLogic

Cache

0.13 m

0.09 m

Cache

CoreLogic

Cache

21

Logic

Memories have better power efficiency compared to logic ~9.9B out of 10B transistors will be used for SRAMs Company with better SRAM design will dominate

Why SRAMs are Important

1.2

1.4

e d I O

N

NMOSPMOS

WL Areat V

=

Taur, Ning

0.4

0.6

0.8

1.0

0.01 0.1 1 10 100

Normalized I OFF

N o r m a

l i z

100X

2X

150nm, 110 C

22

Area is the number one concern minimum sized devices Smaller devices have larger variation Delay variation, stability, leakage is a problem Central limit theorem doesnt hold ( / )

Positive Feedback: Bi-StabilityV i1 V o2V o1 = V i2

V o2 = V i1

Vi1

A

Vo2

o1 i2

23

C

B

Vi1 = Vo2

i2 = o1

Meta-Stability

A V

o 1A

V o 1

C

B

V i 2 =

C

B

V i 2

=

24

Gain should be larger than 1 in the transition region

V i 1 = V o 2

V i 1 = V o 2

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SRAM Memory CellWL

NMOS access transistors

1

BL BLB

25

margins One wordline to access cell Two bit lines (BL, BLB) to carry the data Almost minimum size transistors for small cell area

SRAM Read Operation

0

WL1

Both bit lines are precharged to Vdd

Wordline is fired for one of the cells on bit line

BL BLB11

26

Cell pulls down either BL or BLB Sense amp regenerates the differential signal Data should not flip after read access Driver TR must be stronger than access TR

SRAM Read Operation

27

For high density, large number of cells share bitline andwordline Subarray organization for 32Kb: 128 WLs, 256BLs

Murmann class notes

SRAM Read Operation

bitlinebitline V C

WL

BL

cell I e ayne =

C bitline is large due to large number of cells attached

BLB

SAout

m

28

cell s sma ue o g ens y ce s Vbitline has to be minimized for high speed

< 100mV bitline voltage difference generated by SRAM cell Let the sense amplifier finish the job Increased noise sensitivity, circuit complexity

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SRAM Read Operation: Precharge

29

Vdd-VtnVdd

SRAM Read Operation: Precharge Option (a)

Similar to dynamic logic precharge Balance transistor to equalize bitline voltages Short wordline pulse required to limit bitline swing

Option (b) Pseudo-NMOS type circuit Bitline voltage clamped during read

Option (c) NMOS pullup instead of PMOS

-

30

dd Cant operate at low V dd

VddVdd

Vdd

SRAM Cell Read Margin

Vdd 0 Vx

When cell is not accessed (WL=0) Data is safely kept inside the cell

31

g no se marg n When cell is accessed (WL=V dd )

Access transistor acts as a noise source Data 0 is pulled up to V x Cell data can flip if V x rises above V tn

VDDVDD

VDD

Static Noise Margin

0.2

0.4

0.6

0.8

1

V ( Q B )

VQVQB

E. Seevinck,1987, JSSC

0.6

0.8

1

Q B )

Good SNM0

0 0.2 0.4 0.6 0.8 1V(Q)

32

Destructive read problemThe size of the largest squareenclosed in the butterfly curves= read static noise margin

0

0.2

0.4

0 0.2 0.4 0.6 0.8 1V(Q)

V (

Bad SNM

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CMOS SRAM Analysis (Read)WL

BL

V DD M 4BL

M 5

M 6

M 1V DD V DD V DD

Q = 1Q = 0

C bit C bit

33

Techniques to Improve Read Margin

Cell beta ratio =

(W/L) drv / (W/L) access

J. Rabaey

34

margin But remember, area is the number one constraint in

memory design Increasing cell size a not a good trade off


High V t transistors Internal node on low

side needs to riseto V or more

Virtually never happens when V t is

larger than half V dd Cell is extremely

stable at ultra-lowpower design point SNM low V t

35

relaxed smaller driver and larger access TR can beused for faster readand write

SNM high V t


Boosted cell supply Supply voltage of

Vdd +

ce s g er than outside

Makes driver stronger

than access,suppressing the rise inthe low side

Effectivel im roves

VddVdd

Vdd0

36

the beta ratio

Driver NMOS can bedownsized, decreasingcell size

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SRAM Write OperationWL

1

1

BL BLB01

37

Launch the write data on BL and BLB Word line signal is fired Low bit line value flips cell data Access TR must be stronger than PMOS load

CMOS SRAM Analysis (Write)

M 4

V DD

WL

( )4 / LW PR =

BL = 1 BL = 0

Q = 0Q = 1

M 1

M 5

M 6

V DD

6

38

SRAM Cell Write Margin

0Vdd

VddJ. Rabaey

Vdd 0 0 Vdd

= (W/L) pmos / (W/L) access

39

Access transistor must be stronger than PMOS to pull thebelow the trip point (typical pull-up ratio ~ 1.5)

To avoid cell size increase, correct pull-up ratio achievedby controlling V tn and V tp

Techniques to Improve Write Margin Sizing: access TR vs. PMOS in latch Higher WL voltage for access TR Virtual VDD

Higher voltage

Sizing

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6T-SRAM Layout Until 90nm

V DD

BL BLB

GND

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Compact cellBitlines: M2Wordline: strapped in M3

6T-SRAM Layout From 65nm

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6T versus 4T SRAM

6T SRAM CellSupply current is limitedo e ea age curren o

transistors in the stablestate

4T SRAM Cell

43

g egree ocompactnessHigh power consumption

RAM Variations Many variations to the basic 6T SRAM cell More functionality, smaller cells

True multi-ported cell Content addressable memory (CAM)

4T memory cell 3T memory cell 2T memory cell

44

1T DRAM cell

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Dual Read or Single Write CellWL0WL1

Two wordlines, one for each access transistor BL BLB

45

ma ncrease n ce s ze Can either

read two different cells in one cycle or write to one cell

Multi Port CellWL0

BL0 BLB0WL1

BL1 BLB1

46

ac por as separa e a ress Memory access bandwidth is twice (ideally) Write through: data written can be read by

another port in the very same cycle

Multi-Port RAM Cells Array 7 words deep,

2 wide words,dual port mem

SA0

word j and write

d1d0 to word k

simultaneously:Set SA j=1, and allother SAs=0Set SB =1, and all

SB0

. . . . . .

SA1

SB1

SA7


other SBs=0Sense the values onbus_A0 and bus_A1Write d 1d0 tobus_B0 and bus_B1

b u s _B

0

b u s _A

0

b u s _A

0

b u s _B

0

b u s _B 1

b u s _A 1

b u s _A 1

b u s _B 1

SB7

Content Addressable Memory (CAM) Instead of address, provide data find a match

Applications: cache, physical particle collider

Needs Encoder:Inverse function of decoderTake a one-hot collection of signals and encode them

en

m bits


[Hauck]

coder

n

2n rows

m

addressablememory

cell array

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Content Addressable Memory Cell

Read and write like normal 6T memory cell Match signal is precharged to 1,

ulled to 0 if no matchSend data on bit and data on bit for matchingMatch remains 1 iff all bits in word match

rowselect


[Hauck]

match

bit bit'

Encoders

enco

contentaddressable

memoryer

ce array

rowselect


match

bit bit'

Smaller RAM Cells

Internal nodes dont go toVdd Cell wont work at low Vdd

Need 2 wordlines, read WLand write WL

Can have 1 or 2 bitlines

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degraded

Effective strength of NMOSdriver is reduced

Refresh needed

ea r e Not very small, since it has

more wires

1-T DRAM CellWL

BL

WLWrite 1 Read 1

1

C S

C BL

V DD 2 V T X

sensing

BL

GND

V DD

V DD /2

V DD /2

-

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Write: C S is charged or discharged by asserting WL and BL.Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV.

V BL V PRE V BIT V PREC S

C S C BL+------------= =V

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DRAM Cell Observations1T DRAM requires a sense amplifier for each bit line,

due to charge redistribution read-out.

SRAM cells.The read-out of the 1T DRAM cell is destructive; read

and refresh operations are necessary for correctoperation.

When writing a 1 into a DRAM cell, a threshold

53

.bootstrapping the word lines to a higher value than V DD

Sense Amp Operation

V (1)V BL

D V (1)V PRE

54

t Sense amp activatedWord line activated

1-T DRAM Cell

M1 word

Capacitor

line

Diffusedbit line

Polysilicongate

Polysiliconplate

Metal word line

Poly

SiO 2

Field Oxiden + n +Inversion layerinduced byplate bias

Poly

55

Uses Polysilicon-Diffusion CapacitanceExpensive in Area

Cross-section Layout

Dynamic RAM 1-Transistor Cell: Layout

Spring 2006 EE 5324 - VLSI Design II - Kia Bazargan 56

[Prentice Hall]

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Advanced 1-T DRAM CellsCapacitor dielectric layerCell plate

Word lineInsulating Layer

Cell Plate Si

Capacitor Insulator

Storage Node Poly

Refilling Poly

Si Substrate

IsolationTransfer gateStorage electrode

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Trench Cell Stacked-capacitor Cell

Good References on RAM K. Itoh, VLSI Memory Chip Design , Springer-Verlag

New York, LLC . , . , . , . ,

Review and future prospects of low-voltage RAM circuits , Vol. 47, No. 5/6, 2003, IBM J R&D

R. W. Mann, W. W. Abadeer, M. J. Breitwisch, O. Bula,et al, Ultralow-power SRAM technology , Vol. 47, No. 5/6,2003, IBM J R&D

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59 60

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