Leadership in DSP Technology for Communications...

Leadership in DSP Technology forCommunications Applications

The Star*Core SC140 DSP Core isoptimized for compilability, low power, high

performance, and low system cost

Motorola and Lucent TechnologiesSC140: DSP Technology Leadership

for Communications Applications

Cordless

Video Conferencing

Storage

DSP Applications WirelessHandset

Automotive

Pagers

Home TheaterDigital Cameras

WirelessInfrastructure

Modems



• Lucent ME and Motorola SPS - Proven DSP experts and leadingcommunications systems companies, have partnered to:

— Develop Next Generation Digital Signal Processor Technology

— Focused on Communications Applications

— Cross-license existing DSP architectures, Motorola’s M•CORE™ MCU

• Each company will add the new DSP cores from Star*Core to their arsenal ofSystem-on-a-Chip capabilities

• A collaborative R&D partnership was announced in June 1998, and theStar*Core Joint Design Center opened in November 1998 in Atlanta, GA

• Collaboration began long before the announcement

The Star*Core Alliance



A key buildingblock within astandard orcustomized chip

What is a DSP Core?

DSPCore



Why form an Alliance?

Investm

ent

% of core in product

Demands of the Marketplace- Application specific cores- Optimized compilers- Architecture complexity- Quality baseline tools- Better time to market- Lower cost, power, memory requirements- Systems design

Scale of integration- System-on-a-chip- Complex software: DSP, O/S, Control Code, APIs, standards- Co-processors- Memory size, caching strategies

Collaboration will provide a distinct advantage to Motorola and Lucent



Star*Core Alliance: Benefits to Customers

Scalable CoresBetter application fit

Resources for Frequent ImprovementsBest in class DSP & communications technology

Dual SourcingSupply continuity for very large volume customers

Lucent Motorola

Sophisticated Tools Based on aCommon Programmer’s Modelcode reuse, faster time to market

for more complex systems

Third Party Tools

Optimizing C/C++ Compilers

Common ApplicationSoftware Libraries

RTOS Software

Roadmap

time

perf

orm

ance



Market Opportunity

* Source: Forward Concepts

1997 1998 1999 2000 2001 2002$0

$2

$4

$6

$8

$10

$12

$14

$16

1997 1998 1999 2000 2001 2002

Forecasted DSP Shipments$Billions



Star*Core Partners Lucent and MotorolaPositioned to Shake Up the DSP Industry

• Lucent 25%• Motorola 11%• Texas Instruments 35%• Analog Devices 8% / Intel 0%• All Others 21%

(10 companies)

Total Available Market in 1997= $3.6 Billion

Source: Dataquest

LucentMotorola

TI

ADI/Intel

All Others



Star*Core AllianceSummary of Benefits

Lucent and Motorola

•Sharing of innovative ideas &technology

•Pooled expertise and resources

•Shorter development cycles

•Better quality designs

•Broader support in the market forarchitectures

•Higher volume will attract morethird-party tool and algorithmdevelopers

Customers

Maximize Your SoftwareInvestment

•Better architectures - Efficient compilability - Higher performance - More scalable

•Shorter time to market - High-level languages - More, better development tools - More, better applications

•DSP solutions available from twoleading seminconductor suppliers - Broader range of choice - Not locked into “supplier hotel”

•Multi-sourcing opportunities

End Users

Next generation of DSPsWill Enable

•Universal cellular phones

•More compact and powerfulwireless infrastructure

•Wireless data appliances

•Wireless videoconferencing

•Faster Internet access throughXDSL and cable modems

•Advanced speech recognition

•Advanced home theater systems

… and that’s just the beginning!!!



The Challenge for New DSP Architectures• Deliver on ALL Key Features:

• Compilability, High Performance, Low Power AND Low Cost

• Architectures often trade off one feature for another:– Example: Compilability vs Performance and Cost

• High Performance -- addressed with higher speeds, multiple MAC, ALU units– Discover and exploit parallelism in DSP code

– Need to feed core pipeline with multiple instructions per cycle (Long Execution Set)– Highly parallelized DSP code can efficiently utilize a Long Execution Set

• Low Cost -- largely a function of code density– Rule of thumb: 80% of application code is serial control code executing 20% of time– Remaining 20% of application code is DSP code, running 80% of time– Key to low cost is efficient control code density

– Difficult to achieve with a VLIW approach --> Single Instruction Word is better

• Compilability– Efficiency is the key to wider use of compilers--> minimize cycles, code density (cost)– Easily supported by single-MAC/ALU cores, but trade-off high performance– Optimizing compilers on VLIW-based multi-MAC cores suffer from poor code density



Meeting the Challenge:The Star*Core SC100 Architecture Highlights

✓ Efficient Compilability

– Write 90% of application code efficiently in a high level language (“C”)

✓ High-Performance, Scalable Architecture

– Supports next generation compute-intensive communications applications

– Single, scalable architecture for portable handsets, PDAs, infrastructure...

✓ Low system cost

– Best-in-class code density and efficient core design

✓ Low Power

– Designed for low-voltage implementations (1.5V and 0.9V)



Star*Core SC100 Architecture Highlights

Efficient Compilability

High Performance, Scalable Architecture

Low System Cost

Low Power



SC100 Architecture: Efficient Compilability• What do we mean by “Efficient Compilability?”

– The SC100 architecture allows system developers to write most of theircode in a high level language (“C”, “C++”), while achieving performance,cost, and power consumption characteristics, typical of code written inassembly language.

• The Key:– Distinctive Architecture based on Variable Length Execution Sets (VLES)

• Basic instruction is 16-bits• VLES groups multiple 16-bit instructions based on

– Discovered parallelism, resource scheduling

• Prefix instructions extend 16-bit instruction capabilities for– Additional registers, predication, etc.

• Compiler explicitly encodes single cycle parallelism– One 16-bit execution set for serial control code– Maximum execution set supported by implementation for DSP loops– No alignment restrictions, no NOP padding

– Orthogonal instruction set and programming model (register file)



Instruction 1

Instruction 1 Instruction N

Instruction 1 Instruction NPrefix 1 Prefix M

Execution Set• Single Instruction

• Multiple Instructions

• Single Prefix

• Multiple Prefixes

Instruction 1 Instruction NPrefix 1

Variable Length Execution Sets (VLES)



The SC100 Architecture:High Performance AND Low Cost

• Control code in DSP applications is typically 80% of code, executing20% of time. Thus, only 16-bit instructions are needed. DSP kernelsare 20% of code running 80% of time. Parallelized multiple issueinstructions are needed for DSP code.

• Cycle performance (power, level of integration) and code density (cost)are crucial to customers.

ProgramMemory

SC10016-bit instructionsfor control

DSP parallelism via instruction grouping

SC100 robust instruction set for DSP

SC100 robust instruction set for control



Star*Core SC100 Compiler Delivers• Enables true development of DSP applications utilizing C/C++ HLLs • Performance with respect to code size/cycle count - competitive with assembly code from other DSPs • Control code size comparable to leading microprocessors e.g. M•CORE, ARM7TDMI

• Optimizations enable use of multiple MAC units

• Easy integration of assembly code as needed into C code

• ANSI C/C++ conformance

• Intrinsic function support for ITU/ETSI primitives

• High-level symbolic debugging support for the optimized code



High Level Optimizations

High Level Optimizations

Low Level Transformations

(LLT)

Low Level Transformations

(LLT)

Code GeneratorCode Generator

S1 (Low level representation)Assembly (Loose)

Parallel Assembly (Efficient)

Star*Core SC140 Compiler Flow





High Performance, Scalable Architecture

Low System Cost

Low Power



The SC140 DSP Core: High Performance

• High Performance, Orthogonal, optimized for communications:

– SC140: 4 MAC Implementation --- 1200 MMACs @ 300 Mhz

– Up to 6 instructions (10 RISC) per cycle plus branch -- 3000 RISC MIPS

– Short, 5 stage pipeline

– 16 functional units - 4 MAC, 4 ALU, 4 BFU, BMU, 2 AAU, 1 BRU (branch unit)



Star*Core SC140 Core Block Diagram

Trace Event Unit

Event Detection

Event Counter

EOnCETM Controller

JTAG Controller

Program Sequencer

Branch Unit(8 Loop Registers)

Instruction Dispatcher

Address Registers27 Tot (16 Gen)

Data RegisterFile (16 Gen.)

Instruction Set

ArchitecturePlug-In(s)

AAU AAU MAC1 MAC2 MAC3 MAC4

ALU1 ALU2 ALU3 ALU4

BFU1 BFU2 BFU3 BFU4

JTA

G

P DB

128

PAB

32

AB

A

32

AB

B

32

DB

A 64

DB

B 64

BMU

128

IB

128

-300 MHz @ 1.5 V; Low Power, Static Design-16 Functional Units Total-16 Bit Data, 40 Bit Accumulators

-Single cycle MAC, Integer and fractional data-32 Bit Address, Byte addressable

-One Unified data and program space-Data Register File: 16 40-bit General Purpose Registers

- Address Register File (32-bits, 27 Total, 16 General Purpose)-Also 4 modulo, 4 offset, 2 Stack Pointers, 1 modulo control

-Branch Registers: 8 hardware loop registers in Branch Unit-128 bit VLES

-Up to 6 instructions per clock, including 4 MACS-128 Bit Data Bandwidth

-Up to 8 data words per clock (4.8 GBytes per second)

Data ALU Section

ISA EngineSection

DebugSection

TA

B

TD

B

32 16



Star*Core SC140: Instruction ExamplesHighlight Architecture Flexibility & Performance

• MAC: 4 different MAC instructions in one cycle– mpy d0,d1,d2 macr -d0,d3,d4 impy d5,d6,d7 mac d2,d4,d5

• ALU: 4 different ALU instructions in one cycle– add d0,d1,d2 cmpgt d3,d4 maxm d7,d8 sub d4,d5,d6

• BFU: 4 bit manipulation instructions in one cycle– and d0,d1 asrr #7,d3 asll d2,d7 ror d4

• Many flexible combinations possible...– mpy d0,d1,d2 cmpgt d3,d4 asll d2,d5 insert #5,#4,d6,d7



The SC140 4 MAC Performance AdvantageBenchmark TI C6x TI C54x SC140 Architectural

ImprovementSC140 over C6x

ArchitecturalImprovementSC140 over C54x

Real FIR N/2 N N/4 2x 4x

Complex FIR 2N 4N N 2x 4x

LMS FIR (delayed) 3N 3N N 3x 3x

4 Multiply Biquad 4N 5N 1.5N 2.67x 3.33x

Correlation N/2 2N N/4 2x 8x

Simultaneous DotProduct and Energy(G1 in VSELP)

N 2N N/2 2x 4x

Radix 2 Complex FFT 4N 8N 2N 2x 4xNote: Approximations of benchmarks Sources: TI Web site, Star*Core



The SC140 DSP Core: Scalability

– Multi-processor/Multi-tasking support supports multiple cores on a chip

– Well-defined core architecture supports application accelerators, coprocessors

– Extendable instruction set --> ISA plug-in capability to enable future wirelessstandards more efficiently

– Re-targettable cores can quickly leverage advanced process technologies fromMotorola and Lucent

– Scalable number of MACs/ALUs



Per

form

ance

1999 2000 2001 2002 2003

Star*Core DSP Core RoadmapMultichannelWireless base stationRemote access serverDSL head end

Low Power Terminal/modem/ADSL2.5/3G digital cellular phoneModem/ADSLPDA communicator

Embedded ControlMass storageMotor control

1. MIPS2. Cost3. Power

1. Power2. Cost3. MIPS

1. Cost2. MIPS3. Power

Star*Core140

4 MACs

SC100 GenerationFewer MACs, ALUs

SC100 GenerationMore MACs, ALUs

Advanced Cordless Phones

1. Cost2. Power3. MIPS

ScalableNext-Gen

More MACs, ALUs

Fewer MACs, ALUs





✓High Performance, Scalable Architecture

Low System Cost

Low Power



Star*Core SC140 Delivers Low System CostThrough High Code Density

DSPCore

Memory Subsystem

In System-On-Chip Solutions:

- DSP core is decreasing as % of die area - Memory is increasing as % of die area - Control code often accounts for 80% of overall code size

Conclusions:

- Memory size is the most importantcost factor in many SOC applications.

- Improving memory efficiency is the keyto low cost systems

StarCore SC140 Excels in Code Density (Cost) !!!



0

0.5

1

1.5

2

2.5

3

M•CORE ARM7 SC100 TI 'C54x TI 'C62x

• Benchmarks include a set of complete applications such as DES, JPEG, V42.bis, etc.

Star*Core SC140 Compiled Control Code Density





✓High Performance, Scalable Architecture

✓Low System Cost

Low Power



The SC140 Low Power DSP Core

• Low Power is key for battery-operated devices (handsets, PDAs)– Two components:

• Dynamic - determines active use battery life• Static - determines stand-by battery life

• SC140 Low Power Features– Dynamic:

• Designed specifically to support low voltage operation (1.8V and 0.9V)• Extremely high level of architectural efficiency (in 0-current mode more)

– 4 MACS, ALUS --> Performance/Power Consumption is greater

• Memory efficiency leads to smaller memories, and lower power• Re-targettable cores -- partners can quickly leverage new technologies

– Static:• New power saving modes• Dual threshold transistors to reach 0 static current at high frequency

– The results:• 0.1mA/MIPS @ 1.5V• 0.066mA/MIPS @ 0.9V



Star*Core SC140: The Leader in 3-DimensionsCode Size

Clock CyclesConsumed

Power Dissipation

TI C6x

TI C54x

Star*Core SC140

Performance Cube

Example Application: GSM EFR Vocoder

Sources: Presentations on TI Web site, Star*Core

+ Efficient Compilability

SC140

C6x

C54x

Lower is betterin each dimension



Star*Core SC140:Ideal for Infrastructure and Handsets

• Performance: 2.5G (multiple 100’s MIPS) and 3G (multiple 1000’s MIPS)requirements growing for protocol and for features such as data, still pictures,full video, Internet browsing, etc.

– SC140: 1200 MMACs/3000 RISC MIPS @ 300 MHz• Low Power per Function: New handsets require improvement on current drain

while delivering much greater performance– SC140: 0.066 mA/MIPS at 0.9V– mW/Function: Less than 1.2 mWatts for GSM EFR Vocoder in handset

• Better Code Density to reduce system cost– SC140: Industry best for both DSP algorithms and control code

• Faster Time to Market to meet customer demand for new applications– SC140: DSP & control code can now be done in C/C++ with compiler

• Scalable performance to facilitate tradeoffs with hardware accelerators, co-processors

– IP & systems Expertise from Motorola and Lucent + SC140 core & tools• Applications Software

– SC140: Applications software from communications experts Motorola andLucent. Growing network of 3rd parties



Development Tool Sources

Green HillsSoftware, Inc.

Embedded System

Products, Inc.

AssemblerOptimizerLinkerSimulatorCompiler

MultiEnvironment

RTXC O/S

BaselineTools

IDE/Debugger andProduct Specific

Development Tools

Enea OSE Systems, Inc. OSE O/S

Lucent Toolset

Motorola Toolset



Summary – Star*Core Partners are Poised toShake-up the DSP Industry

• The partnership announced in 1998 is working

• Star*Core DSP cores will address communications and otherapplications, leveraging compilability and scalability

• Star*Core will deliver in 1999

– Its first generation DSP core and related tools

– Star*Core 140 chips & development boards are on schedulefor 4Q99

• Star*Core DSP cores and tools will leverage communicationssystems expertise and DSP experience of both partnercompanies

• Star*Core will design future generation DSP cores using thebest technology from the partners

Leadership in DSP Technology for Communications...

Documents

Transcript of Leadership in DSP Technology for Communications...