LCLS Timing Software and Plan 1

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

LCLS Timing Software and Plan

April 24 2012

Kukhee Kim

ICD Software

SLAC National Accelerator Laboratory

LCLS Timing Software and Plan 2

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

Contents

Current configuration

SLAC specific features

On going issues

Future plan and issues

LCLS Timing Software and Plan 3

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

Timing System Configuration

PN

ET

EV

G

Timing Patternfrom Master Pattern Generator(in old control system)128 bits modifier

VM

TG

119 MHz clock+ 360Hz Fiducialfrom RF timing system

476 MHz main drive line RFwhich carries the 360 Hz trigger modulation

ioc

Fanout

360 Hz fiducial6x32bits modifiers[0_255] event codes +BSA related information

EVRs

from Master Trigger Generator(new system)

LCLS Timing Software and Plan 4

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

Current ConfigurationMaster Pattern Generator (in old control system) generates 128 bits timing pattern (+ beam code + pulse Id) at 360 Hz and broadcasts it on PNET

PNET module in EVG IOC receives the timing information and drives the 360 Hz timing processing

EVG software evaluates the timing pattern from the PNET and makes the extended timing pattern with programmed logic

timeslot n with m Hz

….

Software also generates and transfer the information from EVG to EVR 360Hz pulse Id embedded timestamp

Event codes

BSA information

Software maintains the timing pipeline

LCLS Timing Software and Plan 5

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

Beam Synchronous AcquisitionBeam Synchronous Acquisition (BSA):

Acquire all beam-dependent scalars across multiple IOCs on the same pulse over multiple pulses of a certain kind (not just x-pulses-in-a-row) up to 120Hz.Acquire up to 2800 values per scalar in one acquisition request.Each value of the 2800 values can be an average of up to 1000 values.Each acquisition request can specify:

Beam code (defines project, 1 = LCLS)Machine conditions of interest – rate, TS, permits, etc

Provide constant 1HZ beam-synchronous data for channel archiver and displays

LCLS Timing Software and Plan 6

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

BSA data gethering

Data gathering part consists of the following actions:BSA event definition (EDEF) setup and start request done on the EVG IOC.360hz checking on the EVG IOC with user notification when finished.360hz requests (acquisition control) sent by the EVG IOC to all EVR IOCs via fast fiber optic link.Data checking, averaging, and array update per scalar record per request on the EVR IOCs.

Data on EVR IOC must be available within 7.3 msec after beam or it will be lost, even when beam is less than 120hz. EDEF will finish with arrays that are not complete if this time budget cannot be met.

For an acquisition at full beam rate (ie, 30hz), if data is acquired at a lower rate (ie, 10hz), the array will not be complete. Use rate-limit bits as-needed when setting up the EDEF.

Implementation is all EPICS record-based.

EVR

IOC

EVG

PNET

IOC

BPM FEE

Triggers

Timing Crate

BPM Crate

Data

CA Client

EDEF Flags, Pattern, etc

EDEF Setup CA Client

BSA Data

LCLS Timing Software and Plan 7

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

Pipeline, Pattern & Event Code

Pipeline Advancing in the EVG

Generate New patternat !3 pulses prior!

Step 5

Decide event code list with the !Next1! pattern

Dealing with the next1 patternPipeline index =1 is hard-coded in the database

Fiber connection to EVR

Trigger/Event Generationby the Event Code

Pipeline Advancing in the EVR

EVG EVR

Construct EDEF data (for BSA) from theMOD5 & EDEF Masks

Re-construct EDEF data (for BSA)from the MOD5 & EDEF Masks

LCLS Timing Software and Plan 8

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

BSA & EDEF messageEVG side

EVR side

Modifiers

MOD5 for BSA masks (active)

+

TimeStamp

+ AvgDone, Minor, Major, Init

EDEF masks

Pattern for Next3

Pattern Pipeline

Step 5

Fiber optic connection

EDEF Table

DEDEF 0DEDEF 1

DEDEF 19

DEDEF n Timestamp (active) Timestamp (Init) avgDone flag Severity

Update the EDEF table, after complete the pipeline advancing

EVG&EVR do exactly same processingto update the EDEF table

LCLS Timing Software and Plan 9

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

On going issue

Switch PNET to VMTG (MTG)

Due to the retirement of MPG in old control system

VMTG only provides 360 Hz fiducial + timslot 0 which is synchronized with AC power line

EVG software decided timing information/timing pattern which programmed by the evGui

EVG software also decided pulse Id

Pattern Bit Generator (PABIG) software module will do the timing pattern business in the EVG

Keep use upper level EVG software

LCLS Timing Software and Plan 10

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

Software Stack for EVG

PNETVMTGAcromag DIO EVG

BCS SBI PermBCS Beam Perm 119MHz Clock 360Hz Fiducial TriggerPNET broadcasting

Asyn module VMTG module

EVGDrv/Dev

PABIGGenVarMasterBeamControlBits 0 to 8via CA

HW input bits in PABIGEVG Application

EPICSDB

EDEF reservation for the BSA

PNBN PVs from SoftIOC

SNL program

476MHz Clock

360Hz Trigger

360Hz Fiducial Trigger

2nd NIC

udpComm

mpsCommPNET Task

MPS message(beam destination &Perm)

LCLS Timing Software and Plan 11

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

Switch from PNET to VMTGPNET task need to be delayed ~ 150 usec after the PNET IRQ to wait the MPS message.

PNET IRQ is using HW_TIMER to make the delay

The PNET ISR implement 150 usec delay on the HW_TIMER

The callback for the HW_TIMER releases signal to proceed the PNET Task.

VMTG has configurable IRQ delay

Configure the VMTG IRQ delay as ~570 usec

The VMTG IRQ is occurred at 150 usec after the PNET IRQFiducial

PNET

VMTG

Unknown delay

PNET IRQ

ISR implements the timer

Timer callback releases the signalto the PNET task

PNET task

VMTG IRQ

The ISR releases the signal to the PNET task

~150 usec

~ 570 usec

MPS message arrives somewhere before the signal.

LCLS Timing Software and Plan 12

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

evGui Revolution from text base timing configuration to visual timing configuration

LCLS Timing Software and Plan 13

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

Future Plan and Issues (1)merge to main stream

SLAC timing software has been diverse from community

need to know, what is current status of new driver software

need to know, what is future plan for firmware/register map

need to get clear understanding, what is the SLAC specific features in the software

BSA

Timing Pattern

Pipeline?

LCLS Timing Software and Plan 14

Controls

Timing WorkshopEPICS Collaboration Meeting 2012 @ SLAC

Future Plan and Issues (2)

Support new platform Linux

uTCA

Some other new embedded platformincluding the EVR embedded in a FPGA

Improvement for BSA more performance

more easier/flexible configuration

new requirements from physicists