LC Oscillator

8/3/2019 LC Oscillator

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L.C oscillator Tutorial

J P Silver

E-mail: [email protected]

1 ABSTRACTThis tutorial describes the operation of a basic L.C

oscillator as used in RFIC circuits etc. The pertinent

design parameters are given together with their rele-

vant equations to allow basic hand calculations be-

fore simulation is attempted. The initial design con-

sists of a fixed frequency oscillator that is further

developed into a voltage controlled oscillator (VCO),

by the use of MOS devices configured as varactors.Finally a worked example is given to highlight the

design steps required and CAD simulations are also

described.

2 INTRODUCTIONL.C oscillators are probably the most common type of

oscillator used in RFIC design. They can be designed for

a fixed frequency and variable frequency operation (with

the use of a varactor). The performance of the oscillator

is determined by the Quality factor of the L-C resonator.

Usually, a spiral inductor is used in the resonator and

these have quite low Qs of around 3-5 at 2.5GHz. If a

low-phase noise design is required the inductor can bemade off-chip. The inductor can be either resonated

with the device drain capacitance or by adding a shunt

capacitor (on chip or off).

3 OSCILLATOR DESIGN

PHASE NOISE[1].For a discussion on phase noise read the Phase Noise

Tutorial.

But in summary Leesons equation is given below:-

1Q2f

+12P

FkT=)(L

2

Lmavs

+

+

fm

fcf

fm

fcf om

Usually the phase noise is specified in dBc/Hz ie :-

L = 10LogFkT

2P1 +

2f QdBc / Hz10

avs m L

( )ffc

fm

f fc

fmm

o+

+

2

1

The Leeson equation identifies the most significant

causes of phase noise in oscillators, in particular the key

parameter is the loaded Q of the resonator. We know that

typically in CMOS the loaded Q of a spiral inductor is in

the range 3-5. Therefore, if a tighter phase noise specifi-

cation is required then the inductor will need to be off-

chip.

3.1L-C OCILLATOR OPERATION

The circuit of the L-C oscillator is shown in Figure 1.

M2

L2

Vcc

M1

L1

M3

Itail

C1

Vout1

Vout2

Cross-Coupling

Vbias

Figure 1 Schematic diagram of the cross-coupled

L-C MOS oscillator. M3 sets the currents through

each arm of the differential oscillator, and M1 & M2

provide the negative impedance. The inductors L1 &

L2 may be off-chip (depending on the phase noise

requirement) and the resonating capacitors may be

the drain capacitances of the devices themselves.

Each arm of the oscillator has a L-C tank circuit that

determines the frequency of oscillation and form the

drain loads. Frequency dependant signals at the drains

are then cross-coupled to the other devices gate, which

Resonator Q

Phase perturbation

Flicker effect


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creates a negative impedance of value1/gm at the drain

terminals.

Generally then:

( )

( )f.L.2

Vt-VgsI

IgettoRearrangeQ

f.L.2

I

Vt-Vgs

Therefore,

Vt)-(Vgs

IgmWhere

Q

f.L.2

gm

1

:noscillatioFor

Q

f.L.2inductorofRSeries

D

D

D

D

U

U

Q

=

=

=

To ensure reliable startup, L-C oscillators are designed

to have astartup safety factorof at least 2 ie

UQ

f.L.2p

gm

2 R =>

3.2VARIABLE FREQUENCY OSCILLATOR(VCO)

From the previous section we have seen how cross-

connecting the two transistors gives a negative imped-

ance of 1/gm. We also know that this value has to ex-

ceed the losses of the resonator in order for the circuit to

oscillate.

For this tutorial we shall design an example Vco with the

following specification:

Parameter Specification UnitsCentre Frequency 2.5 GHz

Tuning Bandwidth 500 MHz

Ko >100 MHz/V

Phase noise (10KHz offset) > 70 dBc/Hz

Supply 2.5 V

Power consumption


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However, varactors with a high tuning constant (Ko

(MHz/V) will generate a lot of modulation noise and

may well dominate the phase noise generated by the de-

vice and resonator.

The loaded Q of the resonator, will be determined by the

loaded Q of the inductor and the loaded Q of the

MOSFET varactor (variable capacitor). Each component

can be represented by an ideal reactance with a parallel

resistance representing the loss of the component.

Typical Q values for an on-chip spiral inductor at

2.5GHz is 3 to 5. Therefore, if we wish to use an induc-

tor with a higher Q, we have to consider off-chip induc-

tors. Off-chip inductors are commonly formed using

bond-wires and for completeness of this tutorial designnotes on bond wire inductors will be given.

3.2.1Bond wires as inductors [2]

Larger inductances can be realised with bond-wires that

have Quality (Q) factors an order of magnitude higher

than on-chip spiral inductors.

Note that low Q spiral inductors can still be used for low

phase noise applications or for providing bias to the

varactor(s).

The inductance of a bond wire is given by:

= 75.0

2

2

.L o

r

lLn

l

Where r = radius of wire - typically 0.025mm (1mil)

uo = 4 10-7

(permeability of free-space).

As we go higher in frequency the skin effect becomes

more important and increases the losses of the inductor:

(m)Length

(m)wireofradiusr

74.47x10(S/m)tyConductivi

m,indepthskinWhere

2

1

2R

=

=

==

=

==

l

.

f.

r..r.

l o

We can now calculate the unloaded Q of the inductor

thus:

fr

lLn

R

Lo ...75.0

22r

.Q

==

The graph of Figure 4 shows the inductance of a 1mil

diameter gold bond wire for varying lengths.

Inductance vs Bond Wire Length

0.000

2.0004.000

6.000

8.000

10.000

12.000

14.000

16.000

18.000

0 5 10 15

Length (mm)

Inductance

(nH)

Figure 4 Bond wire inductace (nH) vs Bond wire

length (mm) for a gold 1mil diameter bond wire.

If for example we have a 2mm gold bond wire (of diame-

ter 1mil) then we will have an inductance of2nH .

The associated Q of 2mm bond wire will be around 80 at

a frequency of 2.5GHz a considerable improvement on

an on-chip inductor with a typical Q of between 3 & 5

at 2.5GHz. However, for our example we will assume an

inductor Q of 5 can be realized on-chip.

3.3FREQUENCY CONTROL [3,4]Using bond wires instead of on-chip inductors allows the

design of low phase noise oscillators but makes the fab-

rication more difficult as it is difficult to precisely set the

length of the bond wire. Also for use in Phase LockedLoop (PLL) applications it is necessary to have variable

frequency. To make the fixed frequency oscillator into a

variable frequency oscillator (VCO) we add/incorporate

into the resonator a electronically controlled capacitor

known as a varactor.

In MOS technology we can realise a varactor by con-

necting a FET as a diode and applying a reverse bias to it

as shown in Figure 5.


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Vg

Vcontrol

Bulkconnected toD&S

Vgs

Figure 5 Implementation of a varactor by con-necting together the source, drain and bulk of a

MOS Fet (forming a diode) and applying a re-

verse bias across it.

There are two common connections of the MOS fet as a

diode:

(1) B-S-D connected together, with voltage applied

across the gate and B-S-D connection. If we plot capaci-

tance vs (Vcontrol-Vg = Vgs) then we get the response

shown in Figure 6. To simulate the varactor to deter-

mine the capacitance vs voltage characteristics, the ADSsimulation of the varactor is shown in Figure 12.

The disadvantage of this varactor is that the control volt-

age needs to be kept below weak inversion in order to

keep the capacitance reducing with increased control

voltage.

(2) In the second varactor, the voltage is applied across

the gate and bulk only (S & D unconnected) this is

known as an accumulation varactor and produces the

tuning characteristic shown in Figure 7.

The characteristic is more predictable in that the capaci-tance always falls with increasing control voltage.

Note however, a normal varactors capacitance increases

with increased reverse bias, therefore, it will be impor-

tant to check the phasing of the PLL loop that the VCO

is being used in, otherwise the Vco will go to an end stop

and never lock up!!

Vgs

Cox

Accumulation StrongInversion

Depletion

WeakInversion

ModerateInversion

Cmos

Figure 6 Capacitance variation of a P-mos ca-

pacitor with the bulk, source and drain connected

together as perFigure 5. Voltage is applied across

the gate and B-S-D connection.

Vgs

Cox

Cmos

Figure 7 Capacitance variation of a P-mos

capacitor with voltage applied across the gate

and Bulk connection (The source & drain are

unconnected).


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3.4VARACTOR DESIGN EQUATIONS [5]

For this design we will be using the Accumulationmode varactor, where the source and drain terminals are

unconnected and bias is applied across the gate and bulk

only.

We first need to determine the maximim capacitance of

the varactor shown as Cox in Figure 6 & Figure 7, fol-

lowed by the minimum capacitance (that will allow the

tuning bandwidth to be calculated) and the unloaded Q.

The value of Cox or CMAX is determined by the geometry

of the varactor:

fingersgateofNumberN

&process)14TBCMOSHP(For)(96mE6.9Tox

F/m1084542.8Where

N.

oxT

.W.L3.9.CorCox

O9

12

MAX

=

=

=

=

xo

o

The minimum value of the varactor is approximately

given by:

process)14TBCMOSForF/m9E(

ecapacitancdraingateCWhere

.WCC

11-

gdo

gdoMIN

=

=

To determine the maximum and minimum capacitance

for a range or W/L ratios it is easiest to use simulation.

The ADS schematic ofFigure 12, shows an S-parameter

simulation, measuring Zin. On the resulting simulation

run the following equation has been used to determine

the capacitance in pF.

freq)*)(Imag(Zin1*PI*1E12/(-2C=

Using Table 1 we can select a size of varactor that is

going to resonate with the 2nH on-chip spiral inductor

at 2.5GHz with its middle value capacitance using:

2pF2E

.2.5E2.

1

L

.f2.

1

C9-

2

9

2

=

=

=

Depending on the configuration two varactors are used

end to end across a single inductor (see Figure 13) (And

we need to use 2 times C resonating as capacitors in se-

ries!) or a varactor is connected to each of the two load

inductors (see Figure 14).

For this tutorial we will be simulating both design op-tions.

W

(um)

L

(um)

Cmax

(pF)

Cnom

(pF)

Cmin

(pF)

50 0.6 0.071 0.0775 0.013

100 0.6 0.141 0.0835 0.026

150 0.6 0.211 0.125 0.039

200 0.6 0.282 0.167 0.052

250 0.6 0.352 0.208 0.065

300 0.6 0.423 0.25 0.078

350 0.6 0.493 0.29 0.090

400 0.6 0.564 0.33 0.103450 0.6 0.634 0.375 0.116

500 0.6 0.705 0.430 0.129

550 0.6 0.775 0.459 0.142

600 0.6 0.846 0.50 0.154

650 0.6 0.916 0.54 0.167

700 0.6 0.986 0.583 0.180

750 0.6 1.057 0.625 0.193

800 0.6 1.127 0.667 0.206

850 0.6 1.198 0.709 0.219

900 0.6 1.268 0.749 0.231

950 0.6 1.339 0.792 0.244

1000 0.6 1.409 0.833 0.257

Table 1 Cmax & Cmin for an Accumulation

varactor (Using the HP 14B process) with various

W/L ratios. Note that we can increase the capaci-

tance by increasing the number of gate fingers in

parallel. So to give us a varactor with a nominal

capacitance of 4pF (ie two capacitors in parallel to

give 2pF) we could use a gate width of 500um with

10 fingers = 4.3pF.

Note that the parasitic capacitances of the 1/gm devices

will increase the minimum capacitance of the varactorreducing the tuning range. This can only be evaluated

once the 1/gm device sizes are known.

The simulation of a P-type accumulation varactor

(Where the voltage is applied across the gate and bulk

only (S & D unconnected) with the dimensions of

W=600, L=0.6 and N=5, is shown in Figure 8 with the

resulting capacitance (pF) vs control voltage characteris-

tic shown in Figure 9.


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VARVAR3

L=0.6

W=500

Vcontrl=2.5

EqnVar

MM9_PMOS

MOSFET4

_M=1

Width=W um

Length=L um DC_Feed

DC_Feed1

DC_Feed

DC_Feed2

VAR

VAR2

Vcc=2.5

Fc=2500

EqnVar

V_DCSRC2

Vdc=Vcontrl V

V_DC

SRC1Vdc=Vcc V

TermTerm1

Z=50 Ohm

Num=1

S_Param

SP1

Center=Fc MHz

S-PARAMETERS

Zin

Zin1Zin1=zin(S11,PortZ1)

Zin

N

BSIM3_Model

cmosp

Xl=-1e-7

Xw=0Noic=1.4e-12

Noib=2.4e3

Noia=9.9e18

Em=4.1e7Kt2=0.022

Kt1=-0.11

Uc1=-5.6e-11

Ua1=4.31e-9At=3.3e4

Ute=-1.5

Pv ag=14.4617331Pscbe2=3.078664e-9

Pscbe1=6.898588e10

Pdiblcb=-0.0209265

Pdiblc2=9.858521e-3Pdiblc1=1.300053e-5

Drout=7.988149e-4

Dsub=0.3593017

Etab=8.604543e-3Eta0=0.111002

Cit=0

Cdscd=0

Cdscb=0Cdsc=2.4e-4

Nf actor=0.8428454

Voff =-0.0939754B1=5e-6

B0=4.703171e-6

A1=0

Pags=0.09532Ags=0.2633783

Wketa=8.895347e-3

Lketa=-9.580923e-3

Keta=4.690296e-3Vsat=1.57686e5

Prwb=-0.0733682

Prwg=-4.742166e-3

Prdsw=128.4338259Rdsw=2.552456e3

Delta=0.01

Uc=-5.80218e-11Ub=9.033053e-19

Ua=1.447557e-9

Dv t2=-0.061438

Dv t1=0.5624229Dv t0=3.8366128

Nlx=1.867036e-7

W0=1e-5

K3b=-5K3=96.6543548

Pk2=3.340684e-3

K2=0.0200888

K1=0.3913281Pv th0=1.949468e-3

Vth0=-0.8017536

U0=183.1171264Xj=1.5e-7

Vbm=-3.0

Nch=1.7e17

Dwb=9.587665e-9Dwg=-1.585994e-8

Xpart=0.5

Cgbo=2e-9

Cgdo=2.56e-10Cgso=2.56e-10

Pbswg=0.8

Mjswg=0.1912128

Cjswg=4.256e-11Pbsw=0.8

Pb=0.914212

Mjsw=0.1842521Cjsw=2.002874e-10

Mj=0.4683602

Cj=9.196812e-4

Tox=1.01e-8Wwl=0

Wwn=1

Wln=1

Wl=0Wint=2.151118e-7

Lwl=0

Lwn=1

Lw=0Lln=1

Ll=0

Lint=5.519082e-8Js=0

Rsh=2.2

Capmod=2

Mobmod=1Version=3.1

Idsmod=8

PMOS=yes

ParamSweepSweep1

Step=0.01Stop=5

Start=0

SimInstanceName[6]=

SimInstanceName[5]=SimInstanceName[4]=

SimInstanceName[3]=

SimInstanceName[2]=SimInstanceName[1]="SP1"

SweepVar="Vcontrl"

PARAMETER SWEEP

DC_Block

DC_Block1

DC_Block

DC_Block2

Figure 8 ADS simulation to determine the variation in capacitance of a P-type Accumulation varactor diode

(Where the voltage is applied across the gate and bulk only (S & D unconnected) with the dimensions of

W=600, L=0.6 and N=5. The input impedance is measured by adding the Zin parameter box, to allow calcu-

lation of the capacitance at 2.5GHz. The resulting plot of results is shown in Figure 10.


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m1indep(m1)=plot_vs(C, Vsg)=0.70freq=2.500500GHz

-1.620 m2indep(m2)=plot_vs(C, Vsg)=0.12freq=2.500500GHz

1.850

-2 .4 -2 .2 -2 .0 -1 .8 -1.6 -1 .4 -1 .2 -1. 0 -0. 8 -0 .6 -0 .4 -0 .2 0.0 0 .2 0 .4 0 .6 0 .8 1 .0 1 .2 1 .4 1 .6 1. 8 2. 0 2 .2 2 .4-2.6 2.6

0.15

0.20

0.25

0.30

0.35

0.40

0.45

0.50

0.55

0.60

0.65

0.70

0.10

0.75

Vsg

C

m1

m2

Eqn C=1E12/(-2*PI*(imag(Zin1))*freq)P-MOS Accumulation Varactor diode

C (pF)

Eqn Vsg=2.5-Vcontrl

Figure 9 Resulting simulation plot of the ADS schematic (P-type Accumulation type varactor diode) shown

in Figure 8. The equation C converts the imaginary input impedance (Zin) to capacitance pF


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Finally, we need to calculate the unloaded Q of the

varactor by using the following approximate expression:

( )

Vs/m13.6E).1E136.(1EVs/mtoconvert

process)CMOS14TB(For

/ Vscm1.36EmobilitybulkZeroMUZ

oxMUZ.C'Kp

:bygivenfactorgainKp

ox.LP.C'

)VT-12.Kp.(VgsQ

VTVgsL

W.Kp.

ox.W.LP.C'

12Q

23-2-2-2

22

2mos

mos

==

==

=

=

=

=

process)14TBCMOSHP(For)(96mE6.9Tox

F/m1084542.8Where

F/m3.59EE6.9

.1084542.83.9xoxC'

oxT

.3.9.oroxC'

O9

12

23-

9

12

=

=

==

==

x

o

x

o

2-3-3 uA/V84.3.59E13.6EKp ==

( )

( )35

0.6E.E59.3..2.5E2

(1.25).48E.12

Qmosthen

1.25V2

VddVT-VgsthatassumeweIf

26-39

6-

!

=

==

Note: To maximize the Q of the varactor we need to

keep L as short as possible!

3.5RESONATOR Q & BANDWIDTHThe overall unloaded Q of the resonator will depend on

the loaded Qs of the inductor and varactor. However, if

we minimize the varactor gate length and use on chip

inductors the overall Q will be dominated by the Q of the

inductor:

actorINDres QQQ var

111+=

4.435

1

5

11!+=

resQ

The ADS schematic ofFigure 11 simulates the loaded Q

of the resonator (ie P-type varactor diode and on-chip

inductor). The resulting simulation plot with loaded Q

calculation is shown in Figure 10, showing a similar

loaded Q to the hand calculation.

For this initial design the varactor is connected directly

across the inductor giving the largest tuning range. This

however, may not always be required, as the ko

(MHz/V) will be very large. Ko is one of the variables in

PLL loop calculations and will give a large open loop

gain, which may be undesirable and prove difficult tostabilize the loop. In addition, with such a sensitive VCO

comes the problem of noise on the varactor control line

will modulating on the VCO RF output.

An additional design will be given in this tutorial that

shows how the tuning bandwidth can be reduced, so

lowering Ko.

3.6AMPLIFIER GM CALCULATIONIn order to determine the minimum cross-coupled ampli-

fier negative GM we need to find the loss of the resona-

tor. For this we take the inductance and calculate Req:

"==

=

381.2E.2.5E4.4.2R

exampleourforand.fo.LQ.2R

9-9

eq

eq

Therefore, the minimum Gm required for oscillation is:

DP)or(n

PN

eq

I.L

W2.GM

(10/7)ie1.43benowwillmarginup-startThe

10mS.GMmakemarginsomeusgiveTo

ary VCOcomplimentfor-GMGMGMWhere

7mSGMR

1GM

=

=

+=

>#>

KWhere

Thus we can re-arrange to give the minimum W/L ratio

required to give oscillator:

D

2

2.K.I

gm

L

W=


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Sheet

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We would obviously increase this ratio to give us margin

allowing for lower Q in the resonator (reducing Req) and

so ensure reliable startup and operation over tempera-

ture.

To calculate the gate widths we first have to decide on a

drain current, for this example set ID to 5mA.

m1freq=dB(S(1,1))=-5.152

2.512GHz

1.5 2.0 2.5 3.0 3.5 4.0 4.51.0 5.0

-5

-4

-3

-2

-1

-6

0

freq, GHz

dB(S(1,1

))

m1

m3freq=Qext=4.995

2.512GHz

1.5 2.0 2.5 3.0 3.5 4.0 4.51.0 5.0

1

2

3

4

0

5

freq, GHz

Qext

m3

Eqn Qext=real(Zin1)/(2*pi*freq*2.2e-9)

Figure 10 Frequency response of the resonator

circuit shown in Figure 11. The equation has been

added to determine the loaded Q of the circuit

resulting in a loaded Q of 4.99 compared to the

hand calculation value of 4.44.

3.6.1N devices:

35W58.5E2.171E)0E1(

LW

A/V.s171.7EE645.3.471EMUZn.CoxKp

F/m3.645E9.6E

3.97x8.85E

Tox

o3.97.Cox

m471E).1E471(1Emtoconvert

471cmMUZnox;MUZ.C'Kp

3--6-

23

6-34-

23-

9

12

24-2-2-2

2

=$==

===

===

==

==

3.6.2P devices:

120W200.5E2.49E

)E501(

L

W

A/V.s49e645.3.136eMUZn.CoxKp

F/m3.645e9.6e

3.97x8.85e

Tox

o3.97.Cox

136cmMUZpox;MUZ.C'Kp

3--6-

23

6-34-

23-

9

12

2

=$==

===

===

==

e

Estimation of phase noise performance

( )[ ]

carrierfromoffsetFrequency

resonator.theofresistanceseriesequivalentEffectiveReffresonator.acrossamplitudevoltagePeakV

.oscillatorofresistanceNegative

resonatorofresistanceparallelEquivalent

factorsafetyStartupA

Where

2

.A1k.T.Reff.

A

2

2

Radial

V

L

A

o

='

=

=

=

=

'+

='

From our example A ~ 138/(1/10E-3

) = 1.38.

"===

7.154.4

.2EE5.2.2..2Reff

99

Q

LFo

res

( )

[ ]

( ) ( )[ ]

dBc/Hz6.84

)E44.3log(10dBingetTo

E44.3

2

5.2

E10

E5.2.38.11.7.15.293.1.38E

2

.A1k.T.Reff.

9

9

2

3

923-

2

2

=

=

=

+

'+

='

A

o

V

L


10/18

Sheet

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BSIM3_Model

cmosp

Xl=-1e-7

Xw=0Noic=1.4e-12

Noib=2.4e3

Noia=9.9e18

Em=4.1e7

Kt2=0.022Kt1=-0.11

Uc1=-5.6e-11

Ua1=4.31e-9At=3.3e4

Ute=-1.5

Pv ag=14.4617331Pscbe2=3.078664e-9

Pscbe1=6.898588e10

Pdiblcb=-0.0209265

Pdiblc2=9.858521e-3Pdiblc1=1.300053e-5

Drout=7.988149e-4

Dsub=0.3593017

Etab=8.604543e-3

Eta0=0.111002Cit=0

Cdscd=0

Cdscb=0Cdsc=2.4e-4

Nf actor=0.8428454

Voff =-0.0939754B1=5e-6

B0=4.703171e-6

A1=0

Pags=0.09532Ags=0.2633783

Wketa=8.895347e-3

Lketa=-9.580923e-3

Keta=4.690296e-3

Vsat=1.57686e5Prwb=-0.0733682

Prwg=-4.742166e-3

Prdsw=128.4338259Rdsw=2.552456e3

Delta=0.01

Uc=-5.80218e-11Ub=9.033053e-19

Ua=1.447557e-9

Dv t2=-0.061438

Dv t1=0.5624229Dv t0=3.8366128

Nlx=1.867036e-7

W0=1e-5

K3b=-5

K3=96.6543548Pk2=3.340684e-3

K2=0.0200888

K1=0.3913281Pv th0=1.949468e-3

Vth0=-0.8017536

U0=183.1171264Xj=1.5e-7

Vbm=-3.0

Nch=1.7e17

Dwb=9.587665e-9Dwg=-1.585994e-8

Xpart=0.5

Cgbo=2e-9

Cgdo=2.56e-10

Cgso=2.56e-10Pbswg=0.8

Mjswg=0.1912128


Pb=0.914212

Mjsw=0.1842521Cjsw=2.002874e-10

Mj=0.4683602

Cj=9.196812e-4

Tox=1.01e-8Wwl=0

Wwn=1

Wln=1

Wl=0

Wint=2.151118e-7Lwl=0

Lwn=1

Lw=0Lln=1

Ll=0

Lint=5.519082e-8Js=0

Rsh=2.2

Capmod=2

Mobmod=1Version=3.1

Idsmod=8

PMOS=yes

ZinZin1

Zin1=zin(S11,PortZ1)

Zin

N

S_ParamSP1

CalcGroupDelay=y es

Step=8 MHzStop=5 GHz

Start=1 GHz

S-PARAMETERS

VARVAR1

Bond_Wire=2.2Vcontrol=1.3

EqnVar

MM9_PMOS

MOSFET4

_M=5

Width=500 umLength=0.6 um

INDQL4

Rdc=0.0 Ohm

Mode=proportional to f req

F=2.5 GHzQ=5

L=Bond_Wire nH

TermTerm1

Z=50 Ohm

Num=1

R

R2R=1 kOhm

MM9_PMOS

MOSFET9

_M=5

Width=500 um

Length=0.6 um

V_DC

VDD2

Vdc=Vcontrol

Figure 11 ADS simulation to determine the loaded Q of the resonator circuit. The input impedance is meas-

ured by adding the Zin parameter box. The resulting plot of results is shown in Figure 10.


11/18

Sheet

11 of 18

DC_Feed

DC_Feed2

VAR

VAR2

Vcc=2.5

Fc=2500

EqnVar

V_DCSRC2

Vdc=Vcontrl V

V_DC

SRC1Vdc=Vcc V

TermTerm1

Z=50 Ohm

Num=1

S_Param

SP1

Center=Fc MHz

S-PARAMETERS

VAR

VAR3

L=50

W=10

Vcontrl=2.5

EqnVar

MM9_PMOS

MOSFET4

Width=W um

Length=L um DC_Feed

DC_Feed1

Zin

Zin1Zin1=zin(S11,PortZ1)

Zin

N

BSIM3_Model

cmosp

Xl=-1e-7

Xw=0Noic=1.4e-12

Noib=2.4e3

Noia=9.9e18

Em=4.1e7Kt2=0.022

Kt1=-0.11

Uc1=-5.6e-11

Ua1=4.31e-9At=3.3e4

Ute=-1.5

Pv ag=14.4617331Pscbe2=3.078664e-9

Pscbe1=6.898588e10

Pdiblcb=-0.0209265

Pdiblc2=9.858521e-3Pdiblc1=1.300053e-5

Drout=7.988149e-4

Dsub=0.3593017

Etab=8.604543e-3Eta0=0.111002

Cit=0

Cdscd=0

Cdscb=0Cdsc=2.4e-4

Nf actor=0.8428454

Voff =-0.0939754B1=5e-6

B0=4.703171e-6

A1=0

Pags=0.09532Ags=0.2633783

Wketa=8.895347e-3

Lketa=-9.580923e-3

Keta=4.690296e-3Vsat=1.57686e5

Prwb=-0.0733682

Prwg=-4.742166e-3

Prdsw=128.4338259Rdsw=2.552456e3

Delta=0.01

Uc=-5.80218e-11Ub=9.033053e-19

Ua=1.447557e-9

Dv t2=-0.061438

Dv t1=0.5624229Dv t0=3.8366128

Nlx=1.867036e-7

W0=1e-5

K3b=-5K3=96.6543548

Pk2=3.340684e-3

K2=0.0200888

K1=0.3913281Pv th0=1.949468e-3

Vth0=-0.8017536

U0=183.1171264Xj=1.5e-7

Vbm=-3.0

Nch=1.7e17

Dwb=9.587665e-9Dwg=-1.585994e-8

Xpart=0.5

Cgbo=2e-9

Cgdo=2.56e-10Cgso=2.56e-10

Pbswg=0.8

Mjswg=0.1912128


Pb=0.914212

Mjsw=0.1842521Cjsw=2.002874e-10

Mj=0.4683602

Cj=9.196812e-4

Tox=1.01e-8Wwl=0

Wwn=1

Wln=1

Wl=0Wint=2.151118e-7

Lwl=0

Lwn=1

Lw=0Lln=1

Ll=0

Lint=5.519082e-8Js=0

Rsh=2.2

Capmod=2

Mobmod=1Version=3.1

Idsmod=8

PMOS=yes

ParamSweepSweep1

Step=0.01Stop=5

Start=0

SimInstanceName[6]=

SimInstanceName[5]=SimInstanceName[4]=

SimInstanceName[3]=

SimInstanceName[2]=SimInstanceName[1]="SP1"

SweepVar="Vcontrl"

PARAMETER SWEEP

DC_Block

DC_Block1

DC_BlockDC_Block2

Figure 12 ADS simulation for determining the tuning characteristics of a P-type MOS varactor. In this simu-

lation the bulk, source and drain are connected together to produce the response predicted in Figure 6. The

S-parameter simulation contains a Zin block and we use the imaginary term of this to determine the capaci-

tance of the varactor while sweeping the applied gate-source voltage (Vcontrl).


12/18

Sheet

12 of 18

VDD

vout2

VSS

BSIM3_Model

cmosn

Xl=-1e-7

Xw=0

Em=4.1e7

Kt2=0.022

Kt1=-0.11

Uc1=-5.6e-11

Ub1=-7.61e-18

Ua1=4.31e-9

At=3.3e4

Ute=-1.5

Pvag=0.1945781

Pscbe2=5e-10

Pscbe1=2.541131e10

Pdiblcb=-0.5

Pdiblc2=9.723614e-4

Pdiblc1=2.091364e-3

Pclm=0.7319137

Drout=0.0428851

Dsub=0.751089

Etab=2.603903e-3

Eta0=0.1178659

Cit=0

Cdscd=0

Cdscb=0

Cdsc=2.4e-4

Nfactor=1.2410485

Voff=-0.0850186

B1=5e-6

B0=1.648829e-6

Pags=0.0968

Ags=0.1450882

Wketa=-5.792854e-3

Lketa=-0.0143698

Keta=3.997018e-3

A0=0.9059229

Vsat=1.174604e5

Prwb=-0.0586598

Prwg=0.0182608

Prdsw=-33.9337286

Rdsw=1.28604e3

Delta=0.01

Uc=1.831708e-11

Ub=1.582544e-18

Ua=1e-12

Dvt2=-0.1427458

Dvt1=0.9107896

Dvt0=6.5803089

Nlx=5.28517e-8

W0=1e-5

K3b=1.252205

K3=68.279056

Pk2=9.631217e-3

K2=-0.0316751

K1=0.825917

Pvth0=8.691731e-3

Vth0=0.6701079

U0=433.6065339

Xj=1.5e-7

Vbm=-3.0

Nch=1.7e17

Dwb=1.238214e-8

Dwg=-7.483283e-9

Xpart=0.5

Cgbo=2e-9

Cgdo=2.79e-10

Cgso=2.79e-10

Pbswg=0.99

Mjswg=0.1

Cjswg=2.2346e-10

Pbsw=0.99

Pb=0.99

Mjsw=0.1

Cjsw=4.437149e-10

Mj=0.7549569

Cj=5.067009e-4

Tox=1.01e-8

Tnom=27

Wwl=0

Wwn=1

Ww=0

Wln=1

Wl=0

Wint=2.277646e-7

Lwl=0

Lwn=1

Lw=0

Lln=1

Ll=0

Lint=1.097132e-7

Js=0

Rsh=2.8

Capmod=2

Mobmod=1

Version=3.1

Idsmod=8

NMOS=yes

BSIM3_Model

cmosp

Xl=-1e-7

Xw=0

Noic=1.4e-12

Noib=2.4e3

Noia=9.9e18

Em=4.1e7

Kt2=0.022

Kt1=-0.11

Uc1=-5.6e-11

Ua1=4.31e-9

At=3.3e4

Ute=-1.5

Pvag=14.4617331

Pscbe2=3.078664e-9

Pscbe1=6.898588e10

Pdiblcb=-0.0209265

Pdiblc2=9.858521e-3

Pdiblc1=1.300053e-5

Drout=7.988149e-4

Dsub=0.3593017

Etab=8.604543e-3

Eta0=0.111002

Cit=0

Cdscd=0

Cdscb=0

Cdsc=2.4e-4

Nfactor=0.8428454

Voff=-0.0939754

B1=5e-6

B0=4.703171e-6

A1=0

Pags=0.09532

Ags=0.2633783

Wketa=8.895347e-3

Lketa=-9.580923e-3

Keta=4.690296e-3

Vsat=1.57686e5

Prwb=-0.0733682

Prwg=-4.742166e-3

Prdsw=128.4338259

Rdsw=2.552456e3

Delta=0.01

Uc=-5.80218e-11

Ub=9.033053e-19

Ua=1.447557e-9

Dvt2=-0.061438

Dvt1=0.5624229

Dvt0=3.8366128

Nlx=1.867036e-7

W0=1e-5

K3b=-5

K3=96.6543548

Pk2=3.340684e-3

K2=0.0200888

K1=0.3913281

Pvth0=1.949468e-3

Vth0=-0.8017536

U0=183.1171264

Xj=1.5e-7

Vbm=-3.0

Nch=1.7e17

Dwb=9.587665e-9

Dwg=-1.585994e-8

Xpart=0.5

Cgbo=2e-9

Cgdo=2.56e-10

Cgso=2.56e-10

Pbswg=0.8

Mjswg=0.1912128

Cjswg=4.256e-11

Pbsw=0.8

Pb=0.914212

Mjsw=0.1842521

Cjsw=2.002874e-10

Mj=0.4683602

Cj=9.196812e-4

Tox=1.01e-8

Wwl=0

Wwn=1

Wln=1

Wl=0

Wint=2.151118e-7

Lwl=0

Lwn=1

Lw=0

Lln=1

Ll=0

Lint=5.519082e-8

Js=0

Rsh=2.2

Capmod=2

Mobmod=1

Version=3.1

Idsmod=8

PMOS=yes

HarmonicBalance

HB2

ConvMode=Basic (Fast)

NoiseConMode=yes

Noisecon[1]="NC1"

EquationName[1]=

OscPortName="oscport1"

OscMode=yes

UseKrylov=no

FundOversample=4

Order[1]=5

Freq[1]=2.5 GHz

HARMONIC BALANCE

NoiseCon

NC1

NoiseNode[1]=vout2

PhaseNoise=Phase noise spectrum

CarrierIndex[1]=1

NLNoiseDec=1

NLNoiseStop=1 M Hz

NLNoiseStart=10 Hz

HB NOISE CONTROLLER

VDD

MM9_PMOS

MOSFET11

Width=W um

Length=L um

Model=cmosp

VAR

VAR2

L=1

VDD=1.5

Vcontrol=1.5

W=100

EqnVar

I_DC

SRC2

Idc=3.5 mA

INDQ

L4

Rdc=0.0 Ohm

Mode=proportional to freq

F=2.5 GHz

Q=80

L=2 nH

MM9_PMOS

MOSFET4

Width=500 um

Length=3 um

Model=cmosp

MM9_PMOS

MOSFET9

Width=500 um

Length=3 um

Model=cmosp

OscPort

oscport1

MaxLoopGainStep=

FundIndex=1

Steps=50

NumOctaves=4

Z=1.1 Ohm

V=

INDQ

L2

Rdc=0.0 Ohm


F=2.5 GHz

Q=5

L=2.0 nH

VSSMOSFET_NMOS

MOSFET8

Width=W um

Length=L um

Model=cmosn

VSS

MOSFET_NMOS

MOSFET7

Width=W um

Length=L um

Model=cmosn

VDDMM9_PMOS

MOSFET10

Width=W um

Length=L um

Model=cmosp

DC

DC1

DC

VSSMOSFET_NMOS

MOSFET12

Width=W um

Length=L um

Model=cmosn

I_Probe

IDS V_DC

VDD

Vdc=VDD

V_DC

VDD2

Vdc=Vcontrol

VSS

MOSFET_NMOS

MOSFET13

Width=W um

Length=L um

Model=cmosn

V_DC

VDD1

Vdc=-VDD

Figure 13 ADS simulation of the basic L-C oscillator option 1 using harmonic balance. The OscPort is

used by the harmonic balance simulator, to inject a signal into the circuit to determine the frequency of op-

eration etc. The fundamental oscillating frequency is entered into the harmonic balance simulator and

Oscmode is checked.


13/18

Sheet

13 of 18

VSS

VDD

vout2

V_DCVDD2

Vdc=Vcontrol

BSIM3_Model

cmosn

Xl=-1e-7

Xw=0Em=4.1e7

Kt2=0.022Kt1=-0.11

Uc1=-5.6e-11

Ub1=-7.61e-18

Ua1=4.31e-9At=3.3e4

Ute=-1.5

Pvag=0.1945781Pscbe2=5e-10

Pscbe1=2.541131e10

Pdiblcb=-0.5Pdiblc2=9.723614e-4

Pdiblc1=2.091364e-3

Pclm=0.7319137Drout=0.0428851

Dsub=0.751089Etab=2.603903e-3

Eta0=0.1178659

Cit=0

Cdscd=0Cdscb=0

Cdsc=2.4e-4

Nfac tor=1.2410485Voff =-0.0850186

B1=5e-6

B0=1.648829e-6Pags=0.0968

Ags=0.1450882

Wketa=-5.792854e-3Lketa=-0.0143698

Keta=3.997018e-3A0=0.9059229

Vsat=1.174604e5

Prwb=-0.0586598

Prwg=0.0182608Prdsw=-33.9337286

Rdsw=1.28604e3

Delta=0.01Uc=1.831708e-11

Ub=1.582544e-18

Ua=1e-12Dv t2=-0.1427458

Dv t1=0.9107896

Dv t0=6.5803089Nlx=5.28517e-8

W0=1e-5K3b=1.252205

K3=68.279056

Pk2=9.631217e-3

K2=-0.0316751K1=0.825917

Pvth0=8.691731e-3

Vth0=0.6701079U0=433.6065339

Xj=1.5e-7

Vbm=-3.0Nch=1.7e17

Dwb=1.238214e-8

Dwg=-7.483283e-9Xpart=0.5

Cgbo=2e-9Cgdo=2.79e-10

Cgso=2.79e-10

Pbswg=0.99

Mjswg=0.1Cjswg=2.2346e-10

Pbsw=0.99

Pb=0.99Mjsw=0.1

Cjsw=4.437149e-10

Mj=0.7549569Cj=5.067009e-4

Tox=1.01e-8

Tnom=27Wwl=0

Wwn=1Ww=0

Wln=1

Wl=0

Wint=2.277646e-7Lwl=0

Lwn=1

Lw=0Lln=1

Ll=0

Lint=1.097132e-7Js=0

Rsh=2.8

Capmod=2Mobmod=1

Version=3.1Idsmod=8

NMOS=yes

BSIM3_Model

cmosp

Xl=-1e-7

Xw=0Noic=1.4e-12

Noib=2.4e3

Noia=9.9e18

Em=4.1e7Kt2=0.022

Kt1=-0.11

Uc1=-5.6e-11Ua1=4.31e-9

At=3.3e4

Ute=-1.5Pvag=14.4617331

Pscbe2=3.078664e-9Pscbe1=6.898588e10

Pdiblcb=-0.0209265

Pdiblc2=9.858521e-3Pdiblc1=1.300053e-5

Drout=7.988149e-4

Dsub=0.3593017

Etab=8.604543e-3Eta0=0.111002

Cit=0

Cdscd=0Cdscb=0

Cdsc=2.4e-4

Nfactor=0.8428454Voff =-0.0939754

B1=5e-6B0=4.703171e-6

A1=0

Pags=0.09532Ags=0.2633783

Wketa=8.895347e-3

Lketa=-9.580923e-3

Keta=4.690296e-3Vsat=1.57686e5

Prwb=-0.0733682

Prwg=-4.742166e-3Prdsw=128.4338259

Rdsw=2.552456e3

Delta=0.01Uc=-5.80218e-11

Ub=9.033053e-19Ua=1.447557e-9

Dv t2=-0.061438

Dv t1=0.5624229Dv t0=3.8366128

Nlx=1.867036e-7

W0=1e-5

K3b=-5K3=96.6543548

Pk2=3.340684e-3

K2=0.0200888K1=0.3913281

Pvth0=1.949468e-3

Vth0=-0.8017536U0=183.1171264

Xj=1.5e-7Vbm=-3.0

Nch=1.7e17

Dwb=9.587665e-9Dwg=-1.585994e-8

Xpart=0.5

Cgbo=2e-9

Cgdo=2.56e-10Cgso=2.56e-10

Pbswg=0.8

Mjswg=0.1912128Cjswg=4.256e-11

Pbsw=0.8

Pb=0.914212Mjsw=0.1842521

Cjsw=2.002874e-10Mj=0.4683602

Cj=9.196812e-4

Tox=1.01e-8Wwl=0

Wwn=1

Wln=1

Wl=0Wint=2.151118e-7

Lwl=0

Lwn=1Lw=0

Lln=1

Ll=0Lint=5.519082e-8

Js=0Rsh=2.2

Capmod=2

Mobmod=1Version=3.1

Idsmod=8

PMOS=y es

HarmonicBalanceHB2

ConvMode=Basic (Fast)

NoiseConMode=yes

Noisecon[1]="NC1"EquationName[1]=

OscPortName="oscport1"

OscMode=yesUseKrylov =no

FundOversample=4

Order[1]=5Freq[1]=2.5 GHz

HARMONIC BALANCE

VSS

MOSFET_NMOS

MOSFET11

Width=W umLength=L um

Model=cmosn

NoiseConNC1

NoiseNode[1]=vout2

PhaseNoise=Phase noise spectrumCarrierIndex[1]=1

NLNoiseDec=1

NLNoiseStop=1 MHzNLNoiseStart=10 Hz

HB NOISE CONTROLLER

INDQL4

Rdc=0.0 Ohm


F=2500.0 MHzQ=80

L=2.0 nH

VSSMOSFET_NMOS

MOSFET8

Width=W um

Length=L umModel=cmosn

VSS

MOSFET_NMOSMOSFET7


Model=cmosn

INDQL3

Rdc=0.0 OhmMode=proportional to freq

F=2500.0 MHz

Q=5L=2.0 nH

INDQ

L5

Rdc=0.0 OhmMode=proportional to f req

F=2500.0 MHz

Q=80L=2.0 nH

VSS

MOSFET_NMOS

MOSFET10


Model=cmosn

VARVAR2

L=0.6

VDD=1.5Vcontrol=1

W=40

EqnVar

MM9_PMOS

MOSFET4

Width=700 um

Length=2.4 um

MM9_PMOSMOSFET9

Width=700 um

Length=2.4 um

V_DC

VDDVdc=VDDI_Probe

IDS

DC

DC1

DC

I_DC

SRC2Idc=1100 uA

OscPort

oscport1

MaxLoopGainStep=

FundIndex=1Steps=10

NumOctav es=2

Z=1.1 OhmV=

V_DC

VDD1

Vdc=-VDD

Figure 14 ADS simulation of the basic L-C oscillator option 1 using harmonic balance. The OscPort is

used by the harmonic balance simulator, to inject a signal into the circuit to determine the frequency of op-

eration etc. The fundamental oscillating frequency is entered into the harmonic balance simulator and

Oscmode is checked.


14/18

Sheet

14 of 18

m1harmindex=dBm(HB.vout2)=10.982

1

1 2 3 40 5

-30

-20

-10

0

10

-40

20

harmindex

dBm(HB.vout2)

m1harmindex

012345

HB.freq

0.0000 Hz2.531GHz5.062GHz7.593GHz10.12GHz12.65GHz

100 200 300 400 500 600 7000 800

-0.5

0.0

0.5

1.0

1.5

-1.0

2.0

time, psec

ts(HB.vo

ut2),V

m2noisefreq=pnfm=-75.67 dBc

10.00kHz

1E2 1E3 1E4 1E51E1 1E6

-100

-80

-60

-40

-20

-120

0

noisefreq, Hz

pnfm,

dBc

m2

DC.IDS.i

9.859mA

Figure 15 Resulting plots from the ADS simulation shown in Figure 13. Here the control voltage has been set

to center the VCO on ~ 2.5GHz.


15/18

Sheet

15 of 18


1

1 2 3 40 5

-40

-20

0

-60

20

harmindex

dBm(HB.vout2)

m1 harmindex012345

HB.freq0.0000 Hz2.072GHz4.145GHz6.217GHz8.289GHz10.36GHz

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.90.0 1.0

0.4

0.6

0.8

1.0

1.2

1.4

0.2

1.6

time, nsec

ts(HB.vout2),


10.00kHz

1E2 1E3 1E4 1E51E1 1E6

-120

-100

-80

-60

-40

-140

-20

noisefreq, Hz

pnfm,

dBc

m2

DC.IDS.i

9.859mA


to 2.5V giving a resulting oscillating frequency of ~ 2.07GHz.


1

1 2 3 40 5

-20

-10

0

10

-30

20

harmindex

dBm(HB.vout2)

m1harmindex

012345

HB.freq


100 200 300 400 5000 600

-1

0

1

2

-2

3

time, psec

ts(H

B.vout2),V


10.00kHz

1E2 1E3 1E4 1E51E1 1E6

-100

-80

-60

-40

-20

-120

0

noisefreq, Hz

pnfm,

dBc

m2

DC.IDS.i

9.859mA


to 0V giving a resulting oscillating frequency of ~ 3.47GHz.


16/18

Sheet

16 of 18

3.7REDUCING TUNING BANDWIDTHThe previous VCO was designed for maximum band-

width, by directly connecting the varactor to the induc-tor. If we wish to have a VCO operating over a narrower

bandwidth then we need to swap one of the varactors

with a small value capacitor, such that the varactor ca-

pacitance swing is less dominant. The circuit arrange-

ment for the resonator is shown in Figure 18. The easiest

way to determine the value of the coupling capacitor is to

generate a spreadsheet and enter values of Varactor cou-

pling capacitor as shown in

Table 2 Prediction of VCO tuning bandwidth with the

addition of a coupling capacitor Cc in series with a sin-

gle MOS varactor. In order to achieve a % bandwidth of

~ 10% , the required value of Cc is 0.5pF (This will also

give us some margin). Note the addition of the resonatorcoupling capacitor Cc will alter these values slightly and

some adjustments may need to be made to the resonator

to adjust the center frequency back to 2.5GHz.

INDQ

L4

Rdc=0.0 Ohm


F=2.5 GHz

Q=5

L=6 nH

V_DC

VDD1

Vdc=Vcontrol

R

R1

R=1 kOhm

C

C1

C=0.5 pF

MM9_PMOS

MOSFET9

_M=Fingers

Width=Wv umLength=L um

Model=cmosp

Figure 18 Circuit segment of the L-C Vco showing

the modified resonator section. One of the varac-

tors has been replaced with a small value capaci-

tor to dampen the varactor capacitance swing

and thus reducing the VCO tuning bandwith.

Values for the varactor are _M=5, Wv=500 &

L=0.6 giving a predicted capacitance variation of

1.279pF to 4.613pF.

If we re-adjust L to be 5.5nH and Cc set to 0.6pF the

new maximum and minimum VCO frequencies will be

2401MHz and 2657MHz. This will give a center fre-

quency of 2529MHz and a % tuning bandwidth of

10.2%. This value may well need to be increased to al-

low for temperature effects etc.

Table 2 Prediction of VCO tuning bandwidth

with the addition of a coupling capacitor Cc in

series with a single MOS varactor. In order to

achieve a % bandwidth of ~ 10% , the required

value of Cc is 0.5pF

The plots of the narrow bandwidth Vco with Vcontrol set

to 0V and 2.5V are shown in Figure 19 & Figure 20

Cc

pF Max C Min C Min Freq Max Freq

(MHz) (MHz) (MHz/V) (%)

0.1 0.09787821 0.092748 4644 4771 50.68 2.69

0.15 0.14527609 0.134255 3812 3965 61.35 3.94

0.2 0.19168918 0.172955 3318 3494 70.04 5.14

0.25 0.23714785 0.209124 2983 3177 77.45 6.29

0.3 0.28168125 0.243002 2737 2947 83.93 7.38

0.35 0.32531735 0.2748 2547 2772 89.70 8.43

0.4 0.36808298 0.304705 2395 2632 94.92 9.44

0.45 0.41000395 0.33288 2269 2518 99.67 10.41

0.5 0.45110503 0.359472 2163 2423 104.03 11.34

0.55 0.49141003 0.384609 2073 2343 108.06 12.24

0.6 0.53094188 0.408409 1994 2273 111.81 13.10

0.65 0.56972259 0.430975 1925 2213 115.30 13.93

0.7 0.60777339 0.4524 1864 2160 118.58 14.73

0.75 0.64511467 0.47277 1809 2113 121.66 15.51

0.8 0.68176612 0.49216 1760 2071 124.56 16.26

0.95 0.78776739 0.54511 1637 1968 132.36 18.36

0.9 0.75307455 0.52827 1674 1999 129.89 17.680.95 0.78776739 0.54511 1637 1968 132.36 18.36

1 0.82184215 0.561211 1603 1939 134.70 19.01

Varactor

Network

Tuning Range


17/18

Sheet

17 of 18


1

1 2 3 40 5

-30

-20

-10

0

10

-40

20

harmindex

dBm(HB.vout1)

m1

harmindex

012345

HB.freq


100 200 300 400 500 600 7000 800

-2

-1

0

1

2

-3

3

time, psec

ts(HB.vout1),V


10.00kHz

1E2 1E3 1E4 1E51E1 1E6

-120

-100

-80

-60

-40

-140

-20

noisefreq, Hz

pnfm,

dBc

m2

DC.IDS.i

9.859mA

Narrow bandwidth L-C VCO with Vcontrol set to 0V

Figure 19 Prediction of the narrow band L-C VCO performance at a Vcontrol set to 0V.


1

1 2 3 40 5

-20

-10

0

10

-30

20

harmindex

dBm(HB.vout1

m1

harmindex

012345

HB.freq


100 200 300 400 500 600 700 8000 900

-1

0

1

2

-2

3

time, psec

ts(H

B.vout1),V


10.00kHz

1E2 1E3 1E4 1E51E1 1E6

-120

-100

-80

-60

-40

-140

-20

noi sefreq, Hz

pnfm,

dBc

m2

DC.IDS.i

9.859mA

Narrow bandwidth L-C VCO with Vcontrol set to 2.5V

Figure 20 Prediction of the narrow band L-C VCO performance at a Vcontrol set to 2.5V.


18/18

Sheet

18 of 18

4 CONCLUSION

This tutorial described the small signal operation of a L-C oscillator. The relevant design theory was given to-

gether with several worked examples, both fixed fre-

quency and voltage controlled versions.

Harmonic balance ADS simulations were given to simu-

late the circuits, using the hand calculations derived in

the examples to predict, output frequency (and harmon-

ics), output power and phase noise performance.

It was shown that in order to achieve good phase noise

performance the use of low Q on-chip inductors was to

be avoided, opting instead for high Q bond-wire induc-

tors off-chip.

The first VCO was designed for maximum tuning range

by connecting a pair of varactors directly across the in-

ductor. The resulting tuning bandwidth was 55% (ie 2.07

to 3.47GHz), centred on 2.5GHz.

The step by step design of this Vco showed how to de-

sign the resonator and calculate its loaded Q (and hence

determine the VCO phase noise) and its RF loss. With

the knowledge of the loss of the resonator, the gms of

the reflection amplifier devices could be determined to

ensure reliable oscillation (with some margin).

The predicted performance of the wide-band oscillator is

shown in Table 3.

Parameter Predicted

Result

Units

Frequency band-

width

2.07 3.47 GHz

Phase Noise > 75 dBc/Hz @

10KHz

Tuning Bandwidth 55 %

O/P Power >5 dBm

Power Consumption ~ 100 mW

2nd Harmonic >10 dBc

Ko ~500 MHz/V

Table 3 Predicted performance of the wide-

band L-C VCO.

The second VCO example was designed to have a

greatly reduced bandwidth (~10%), thus lowering Ko to

around 100MHz/V, giving a tuning range of 2.401GHz

to 2.667GHz centred on 2.532GHz.

The predicted performance of the narrow-band oscillator

is shown in Table 4. In both cases the harmonic contentis quite high and so a buffer stage with a tuned output

will be required to improve this to a more acceptable

20dc or so.

Parameter Predicted

Result

Units

Frequency band-

width

2.401 2.667 GHz

Phase Noise > 83 dBc/Hz @

10KHz

Tuning Bandwidth 10.5 %

O/P Power >15 dBm

Power Consumption ~ 100 mW

2nd

Harmonic >10 dBc

Ko ~100 MHz/V

Table 4 Predicted performance of the narrow-

band L-C VCO.

5 REFERENCES[1] Oscillator Design and Simulation, Randall W Rhea,

1995, Noble Publishing, ISBN 1-884932-30-4, p111-

131.

[2] Thomas Lee, The Design of CMOS Radio-

Frequency Integrated circuits, Cambridge University

Press, second edition 2004, ISBN 0-521-835389-9,

p145.

[3] P Andreani & S Mattisson, A 1.8GHz CMOS VCO

Tuned by an Accumulation-Mode MOS Varactor. Com-

petence Center for Circuit Design, Dept of Applied Elec-

tronics, Lund University, Sweden. In Proceedings of

ISCAS 2000, Vol. 1, pp. 315-318, May 2000.

[4] W.Wong, P.Hui, Z.chen, K.Lau, P.Chan, P.Ko, A

Wide Tuning Range Gated Varactor, IEEE Journal of

Solid-State Circuits, Vol. 35, No 5, May 2000.

[5] R. Jacob Baker, H Li, D Boyce, CMOS Circuit De-

sign, Layout and Simulation, Wiley Interscience, 2004,

ISBN 0-471-70055-X.

LC Oscillator

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