21LAYOUT DESIGN RULESPHYSICAL LAYER: prescription for preparing photomasks used in fabrication of ICs.

Specify to the designer geometric constraints on the layout artwork so thatpatterns on the processed wafer will preserve the intended circuit topologyand component/feature geometries of the design.

PURPOSE: realize fabricated circuits optimum yield in smallest area possible withoutcompromising the reliability of the circuit.

DESIGN RULE WAIVER: any significant and/or frequent departure from designrules.

TWO TYPES OF DESIGN RULES:

a. line widths and separations

b. interlayer registration

DESIGN RULE SPECS:

a. 'micron' rules - minimum feature sizes and spacings in absolute dimensions µm units(normal spec in industry)

b. scalable 'lambda (λ)' rules - minimum feature sizes and spacings in scalable dimensions interms of a single parameter λ (popularized by Mead and Conway and permits first orderscaling; limited to narrow range of dimensions; tend to be conservative.)

Kenneth R. Laker, University of Pennsylvania

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LAYOUT DESIGN RULES

The Design Process can be Abstracted to Manageable Number of Layout Levels that Representthe Physical Features on the Processed Silicon Wafer, i.e.

-> Two different substrates (i.e. original substrate + well or twin wells)

-> Doped regions p- and n- transistor forming materials (e.g. sources and drains)

-> Transistor gate electrodes

-> Interconnect paths

-> Interlayer contacts

Kenneth R. Laker, University of Pennsylvania

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A1 = 10λ

A2 = 6λ

wells atsamepotential

wells atdifferentpotential

A2 = 8λ

B1 = 3λ

B2 = 3λ

n-Well

p+

Gate Oxide

Field OxideMetal 1

Contact/via

COLOR LEGEND

Metal 3

Metal 2

p-Welln+

Polysilicon

B3 = 5λB4 = 3λ

B5 = 5λB6 = 3λ

C1 = 2λ

C2 = 2λ

C3 = 1λC4 = 2λ

CMOS N-WELL DESIGN RULES

C5 = 3λ

Kenneth R. Laker, University of Pennsylvania

A- N-WELL RULES

B- ACTIVE RULES

C- POLY RULES

24n-Well

p+

Gate OxideField OxideMetal 1

Contact/via

COLOR LEGEND

Metal 3

Metal 2

p-Welln+

Polysilicon

E1 = 2λ

E2 = 2λ

E5 = 1λ

E6 = 1λ

E3 = 2λ

E4 = 1λ

F1 = 3λ

F2 = 3λ

G2 = 3λ

G1 = 2λ

G4 = 1λ

G3 = 1λ

H1 = 3λ

H2 = 4λ

J1 = 8λ

J2 = 5λ

I2 = 3λ

I1 = 2λ

J2 = 2λ

J3 = 2λ

E7 = 1λ

E9 = 6λE8 = 3λ

E10 = 3λ

Kenneth R. Laker, University of Pennsylvania

E- CONTACT RULES

G- VIA RULES

F- METAL 1RULES

J- METAL 2RULES

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p+ p+

p+ drawn p+ region

p+ processed p+ region

drawn poly region

processed poly region

over-etched poly shrinks

source, drain short

diffusion bloats

p+ p+

gate extension (C4)

EFFECT OF INSUFFICENT GATE EXTENSION

Kenneth R. Laker, University of Pennsylvania

C- POLY RULE Violation!

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EFFECT OF INSUFFICENT SOURCE-DRAIN EXTENSION

processed poly region

diffusion mask isshifted left p+ drawn p+ region

p+ processed p+ region

drawn poly region

contact

p+

p+

source

drain

gate

poly mask isshifted right

mask misalignmentchanges length and/orwidth of device andsometimes completelyeleminates it.

Kenneth R. Laker, University of Pennsylvania

Another C- POLY RULE Violation!

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TECHNOLOGY RELATED CAD ISSUES

TWO BASIC CHECKS MUST BE COMPLETED TO ENSURE THE MASK DATBASEDEVELOPED IN LAYOUT CAN BE TURNED INTO A WORKING CHIP:

a. To verify specified Design Rules have been obeyed

(DESIGN RULE CHECK or DRC)

b. To verify masks produce correct interconnected set of circuit elements

(MASK CIRCUIT-EXTRACTION)

Kenneth R. Laker, University of Pennsylvania

Functionality & performance specs

Stick diagram layout

Initial sizing of transistors

Estimate parasitic capacitances

Circuit topology or schematic

Mask layout design

Design Rule Check (DRC)

Circuit & parasitic extraction

Circuit simulation

Layout CompleteOK

Resize &Modify

ImprovePerformance

TYPICAL DESIGN FLOWFOR THE PRODUCTIONOF AN IC MASK SET

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