Layout Considerations of Non-Isolated Switching Mode Power Supply

LTC Company ConfidentialHenry J. Zhang, Oct. 2003 FAE Meeting [email protected], 3863

Layout Considerations of Non-Isolated Switching Mode Power Supply

Presented by

Henry ZhangPower Business Unit

Linear Technology Corp.Oct. 2003


1. General Discussion


Plan of the Power Supply Layout

• In the system, power supply should be close to its load devices.

• Cooling fan should be close to the supply to limit its component thermal stress.

• Select the right number of layers and copper thickness

• The large size passive components (inductors, bulk capacitors) should not block air flow to power MOSFETs

• Power supply designer should always works closely with PCB designer on the critical layout design


4-Layer PCB – Layer Placement

Layer #1 – Power Component

Layer #3 – GND

Layer #2 – Small Signal

Layer #4 – Small signal / controller

Undesired

High current loopPulsating current loop

Power

GNDPCB capacitance

Signal


Layer #2 – GND


Layer #4 – Small signal / controller

Desired

• Place ground or DC voltage layer between power layer and small signal layer


6-Layer PCB - Layer Placement


Layer #2 – GND plane


Layer #4 – Small SignalLayer #5 – DC Voltage or GND plane

Layer #6 – Power Component / Controller

DesiredUndesired


Layer #2 – Small signal

Layer #3 – GND plane

Layer #4 – DC Voltage or GND planeLayer #5 – Small signal

Layer #6 – Power Component / Controller

• DC power and ground planes function as AC reference planes.

• As a general rule, the reference planes of a multi-layer PCB design should not be segmented.


Small Signal Traces on Reference Layer

• If the small signal traces have to be routed on the reference layer, use short traces with proper direction:

PWM IC MOSFET

Coupled ACcurrent return path

Reference Layer

current

Reference Layer

current

Desired Undesired


Copper Thickness and PCB Resistance

Resistance of copper:][][

][]/)[()(

cmThicknesscmWidth

cmLengthcmTSTR

)]20(0039.01[10724.1)( 6 TTSCopper resistivity (/cm):

T – Copper temperature in oC

][][

][54.2

1000]/)[(

milsThicknessmilsWidth

milsLengthcmmils

cmTS

Example: 1 Oz copper (1.4 mil thick), 0.5 inch wide (500mils), 2 inches long (2000mils), at 70 oC with 20A current:

Rcopper = 2.3 m, Vcopper=46mV, Ploss=0.92W

High current application - Recommend 2 oz or higher for external power layers


2. DC/DC Converter Power Stage Layout


Buck Converter Current Paths

Continuous Current

Pulsating Current

High dv/dt node

CHF

• Identify the continuous and pulsating current paths• Pay special attention to pulsating current paths and high dv/dt switching node

VIN+

ESRin

VinCin

ST

SB

LF

CoR VoD

ESRo

SW

PGND


VIN+

SWLF

PGND

Parasitic Inductance in the Current Pathsand Example Layout (Buck)

Minimize this loop area

0.1uF – 10uFCeramic Capacitor

CHF

D

ST SBST

SB D

SW

VIN+

PGND

Trace Inductance

CHF

• Minimize loop between HF capacitor and MOSFETs• It is desirable to keep CHF, top FET and bottom FET on the same layer• Use multiple vias for power connection


Boost Converter Current Paths

Continue Current

Pulsating Current

CHF

D

SB

LF

CIN

Load

Vo

High dv/dt node

Co

VIN

Vo+SW

PGND

• Minimize the critical pulsating current loop on the output side


Output Noise Decoupling Capacitor (Boost)

PGND

Minimize this loop area

Vo+

SW

0.1uF – 10uFCeramic Capacitor

SB

D

CHF

LF

CHF

D

SB

SW

PGND

LF

(a) (b)

• Minimize the critical pulsating current loop on the output side


12V-to-2.5V/30A LTC3729 Supply Layout Example

(a)

VO+ (2.5V)

VO+ (2.5V)

VIN+ (12V)

VIN+

GND

LTC3729

LF1

Co

Co

CIN

QT

SW1

QB

SW2

GND


Noise Problem @ Heavy Load

Io = 0A Io >= 13.3 A

vSW1

vSW2

iLF1

(b) (c)


VO+ (2.5V)

VO+ (2.5V)

VIN+ (12V)

VIN+

GND

LTC3729

LF1

Co

Co

CIN

QT

SW1

QB

SW2

GND

VO+ (2.5V)

VO+ (2.5V)

VIN+ (12V)

VIN+

GND

LTC3729

LF1

Co

Co

CIN

QT

SW1

QB

SW2

GND

Input Ceramic Capacitors Make a Difference

Io = 0A Io = 30 A(a)

Add1uF/16V/X7R

vSW1

vSW2

iLF1

(b) (c)


Land Patterns of Power Components

Undesired

Connected Via

• Use wide / short copper trace for power components• Use multiple vias for inter-layer connections• Avoid improper use of “thermal relief” • Minimize resistance and inductance

Desired

C R/C/D/L

R/C/D/L

FET

C

+ -

+ -

Connected Via


3.3V/40A LTC3729 Layout Design Example

+C44.7uF16V

4 x 330uF/4VSanyo POSCAP

R3

10

R13

100

Signal Ground

D3MBRS340

1

2 3

J1

L1 0.56uH

R1010

R18.06K

L2 0.56uH

QB22xSi7856DP

4

1

5 6 7 8

2 3

CHF11uF

Power Ground

R910

GND

C9 0.47uF

C1180pF

C70.1uF

U1

LTC3929EG

1 23

4

56

7

8

9

10

11121314

15

19

20

21

22

23

24

252627

28

16

17

18

RUN/SS SENSE1+SENSE1-

EAIN

PLLIFLTRPLLIN

N/C

ITH

SGND

VDIFFOUT

VOS-VOS+

SENSE2-SENSE2+

PGOOD

BG2

PGND

INTVCC

EXTVCC

BG1

VIN

BOOST1SW1TG1

NC

TG2

SW2

BOOST2

C51uF10V

Cthp120pF

QB12xSi7856DP

4

1

5 6 7 8

2 3

VOUT

Rth14K

CHF21uF

C6 0.47uF

+COUT1

Csen11000pF

R12

100

D1MBRS340

12 3

QT2

Si7860DP

4

1

5 6 7 8

2 3

3.3V@40A

J3

J5

R8

100

C14 0.1uF

Csen21000pF

VSEN+

D2 BAT54A

SOT-23

1

23

VSEN-

VIN

Rsen2

0.002 OHM

12V

R11

100

C2

220pF

J4

Cth560pF

J2

QT1Si7860DP

4

1

5 6 7 8

2 3Rsen1

0.002 OHM

INTVCC100UF/16V

+CIN

R2

25.5K

High Current Trace


Examples of a 2-Phase DC/DC Power Stage

Vo

SW1

GND

QT1

QB1 QB1CHF1

L2

L1

Rsen2

Rsen1

Cout

Cout

DCIN

Vin

InternalGND Layer

VIN

Vo

SW1

SW2

GND

GND GND

GND

QT1

QB1 QB1

QB2 QB2

QT2

CHF1

CHF2

L1

L2

Rsen1

Rsen2

Cout

Cout

Cout

D

D

InternalGND Layer

CIN

Air Flow


Separation of Input Paths Among Supplies

Cin DC/DC#1

DC/DC#2

PGND

Cin

DC/DC#1

PGNDDC/DC

#2

PGND

PGND

Undesired Desired

RPCB

RPCB1

RPCB2


3. Layout of the Controller and MOSFET Drivers


Decoupling Capacitor and Separated Grounds

Shortest Distance

SEN2-

SEN2+RSENSE

SEN1+

SEN1-RSENSE

ITH

SGND PGND

INTVCC

TG1

SW1

BG1

TG2

BG2

SW2

LTC3729

SGND Island

PGNDPlane

R

RC

C

C

C

R

R

RUN/SS

C EAIN

VDIFF


Signal Ground and Power Ground

• Components connected to following pins use SGND:

- EAIN, RUN/SS, ITH, UVADJ, PHAMD, PLLIN, PLLFTR, FCB, CLKOUT

•Components connected to following pins use PGND:

- BOOST, +5V, PGND

•The SGND and PGND can be tied together underneath the IC.


QFN Package Controller Layout

• Exposed SGND pad must be soldered to PCB• Use multiple vias to connect SGND pad to both SGND and PGND layers• PGND pin also connects to SGND pad underneath the IC

SGND

PGND

INTVCC C

PGND

Vias

Vias

LTC3731

SGNDPGND

Example


PGND

INTVCC

TG1

SW1

BG1

LTC3729

PGNDPlane

C

QT

QB

Automatically coupled AC ground return current

BOOST1

Gate Driver Traces

Route together


IC Signal Trace Width

Following are the trace width values we use in Polyphase demo board:

20 mils – TG, BG, SW

25 mils - +5V, Vcc, PGND

15 mils – Current sensing, feedback, ITH, etc.

10 mils – Short traces that directly connected to IC pads


Current Sensing Traces

SENSE-

SENSE+

RSENSE

LTC3729

CR

R

LF

Vo+

• Kevin sensing of the current signal• Keep current sensing traces away from noisy traces / copper area or use ground layer for shielding.

This via should NOTtouch any other internal Vo+copper plane.

Direct trace connection.Do NOT use via.


Sensitive Traces and Noisy Traces• Most sensitive traces:

Current sensing (SENSE+/-), EAIN, ITH, SGND

-Sense+ / - traces for each channel should be routed together With minimum trace spacing. The filter capacitor should be as close toIC pins as possible. The filter resistor should be close to filter capacitor. - Keep sensitive traces away from noisy traces.

• Sensitive traces:

Vos+/-, DIFFOUT, PLLFTR, CLKOUT

• Most noisy traces: SW, TG, BOOST, BG

-CLKOUT is a sensitive trace but it is also a noisy trace. So keep it away from other small signal sensitive traces.

-Keep them away from sensitive traces. -Avoid overlapping between large SW copper area and sensitive traces in two neighborhood layers.- For each channel, route the SW and TG trace together with minimum space.


Summary - Layout Checklist

• Plan of the layout:

– Location of the supply / load / bulk capacitors– # of layers / layer placement / copper thickness

• Power stage layout:– Power component placement– Power component land patterns– Identify pulsating current paths– Decouple capacitor close to MOSFET– Short / wide copper trace and multiple vias for high current

• Controller circuit layout:– Decoupling capacitors close to pins– Separate signal / power grounds– Current sensing– De-couple sensitive and noisy traces– Gate driver traces– Select proper trace width

Layout Considerations of Non-Isolated Switching Mode Power Supply

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