Laurent LocatelliLHCb CERN

Calo commissioning meeting16th April 2008

Trigger Validation BoardPVSS control status

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Trigger Validation Board

Actual implementation (1):

rising/falling edge and delays (in clock cycles) (R/W)for PSSPD0-7 and ECAL0-7 front clocks in EPPI FPGA for PSSPD0-7, ECAL0-7 and HCAL0-7 front clocks in HCAL FPGA

BXID offset (R/W), idle time (R/W), card number (R) in EPPI and HCAL FPGAs control LASER (R/W) in EPPI FPGA GOL control (R/W) in EPPI and HCAL FPGAs delay chip (0 – 24 ns) (R/W) LUT loading (W) in EPPI and HCAL FPGAs Notice: Each group of 6 bytes is transmitted using an individual i2c call. HCAL LUT: 512 i2c calls => ~1min EPPI LUT: 256 i2c calls => ~30sec => quite long process (~1.5min for each TVB)

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Possibility to save settings into files for reuse.Configuration can be performed from files for each TVB individually.Also included in recipes for general FSM configuration.

Trigger Validation Board

Actual implementation (2):

GOL control (R/W) in optical mezzaninefor global pi0, local pi0, photon and electron (EPPI)for HCAL0-3 (HCAL)

information about FPGA (type, firmware, date) for EPPI and HCAL FPGAs (R) Input Spy RAM (R) for EPPI and HCAL FPGAs - Spy RAM entirely read by 256 i2c calls => quite long process

Problem: Spy RAM internal address incremented automatically and goes from 0 to 254 instead of 255 (=> only 255 i2c calls ???) temperature sensors under mezzanine and between FPGAs

1. temperature (R): - reading function implemented properly.

- Oracle archiving and monitoring as a function of time in progress.2. thresholds (R/W) and configuration (R/W):

- reading and writing functions implemented properly. - not yet included in recipes for general FSM configuration.

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What remains to be implemented:

Output Spy RAM (R) for EPPI and HCAL FPGAs triple voting (R) in EPPI and HCAL FPGAs

Trigger Validation Board

Optimization of LUT loading:

1. fwSpecs_write function with a filename as data parameter developed by Clara first tested on delay chip because registers are R/W, but only 3 bytes.

function originally developed for the LUT (read only): not good for read back registers

=> conflict in datapoints between reading and writing, causes overwriting of the setting file when reading!!! “quick and dirty” trick (dpSetWait) introduced in order to allow read back

=> seems OK when setting the delays for each TVB individually=> problems occur when included in general FSM configuration

as the trick causes a second writing of the datapoint, but with the last

data in the SPECS server memory (quite random...)

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2. Other problem with fwSpecs_write function with a filename as data parameter for the LUT:

HCAL (resp. EPPI) FPGA expects 512 (resp. 256) i2c calls with data frame:

master ID + slave addr. + bus i2c + START + i2c reg. addr. + 6 bytes + STOP

The function read the bytes in the file and transmit them successively. The transmission

follows the SPECS “rules”, i.e. 16 bytes are sent and then the STOP condition.

Trigger Validation Board

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New fwSpecs_write function with a filename as data parameter which:

allows read back register without datapoints conflict counts 6 bytes before sending a STOP condition

implemented in new SPECS version 3.6. Has to be tested on TVB individually and in the general FSM configuration.

Future plans:

- New firmware v7.0 of EPPI and HCAL FPGAs which allows to read back the LUT under development. - Tests on HCAL FPGA are currently performed on a test bench in Annecy. - See changes with respect to actual version 6.0 and first results in next presentation.

Crosscheck with CAT: A data frame is transmitted from output spy RAM of FEBs in input to the TVB. 1. All LUT are set to 1 with CAT => spy output buffers (with CAT) after calculation 2. All LUT are set to 0 with PVSS => spy output buffers (with CAT) after calculation

=> result should be zero but it is not the case, function not efficient

PANELS

Trigger Validation Board

EPPI FPGA panel: HCAL FPGA panel:

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Trigger Validation Board

Delay chip and LUT panel:

GOL panel:

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Trigger Validation Board

EPPI and HCAL FPGAs informations (type, firmware, date) and mezzanine flags panel:

Temperatures panel:

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Trigger Validation Board

EPPI Spy RAM panel:

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HCAL Spy RAM panel:

BACKUP

Trigger Validation Board

Optimization of LUT loading (1):fwSpecs_write function with a filename as data parameter developed by Clara:

first tested on delay chip because registers are R/W but function originally developed for the LUT (read only): not good for read

back registers=> conflict in datapoints between reading and writing,

causes overwriting of the setting file when reading!!! “quick and dirty” trick (dpSetWait) introduced in order to allow read back

=> seems OK when setting the delays for each TVB individually=> problems occur when included in general FSM configuration

as the trick causes a second writing of the datapoint, but with the last

data in the SPECS server memory (quite random...)

Write and read with filename as parameter properly implemented in new SPECS version 3.6 but has to be tested on TVB individually and in general FSM configuration.

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Trigger Validation Board

Optimization of LUT loading (2):Other problem encountered with fwSpecs_write function with a filename as data parameter:

HCAL (resp. EPPI) FPGA expects 512 (resp. 256) i2c calls with data frame:

master ID + slave addr. + Bus i2c + START + i2c reg. addr. + 6 bytes + STOP

The function read the bytes in the file and transmit them successively. The transmission

follows the SPECS “rules”, i.e. 16 bytes are sent and then the STOP condition.

New write function (with filename as parameter) which counts 6 bytes before sending a STOP condition implemented in new SPECS version 3.6. Has to be tested on TVB individually and in general FSM configuration.

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