Latest ieee projects list
5
Silicon Mentor VLSI Projects Topic For M.tech/PhD [email protected] +91-8130809758 www.siliconmentor.com
-
Upload
silicon-mentor -
Category
Technology
-
view
231 -
download
1
Transcript of Latest ieee projects list
Silicon Mentor
VLSI Projects Topic
For
M.tech/PhD
[email protected] +91-8130809758 www.siliconmentor.com
IEEE Projects
• Modeling of analog circuits for mixed-signal design simulations using Verilog.
• Design & Analysis of a Capacitor-Less CMOS Active Feedback LDO With improvement of Slew-Rate for On-Chip Application.
• Realization of Low voltage integrators for CMOS filters through current mode techniques .
• Design of analog standard cell for low frequency CMOS filters design for low power applications.
• Design & performance analysis of CMOS switched current ladder filter.
• A Novel approach for designing of current comparator for current mode Analog to Digital converter.
• Design of CMOS current comparator using offset compensation technique.
[email protected] +91-8130809758 www.siliconmentor.com
IEEE Projects
• Implementation of differential CMOS OTA through the bulk-driven technique at 0.8 volts
• Design and Analysis of ADC using SAR architecture at 130 nm CMOS technology.
• A high speed Analog to Digital converter using Fat tree encoder and Switched capacitor.
• Study of single-ended inductively-degenerated common-source cascode LNA using a 180nm CMOS technology.
• Design 7 Study of dual band LNA at 90nm Process technology.
• Design and Analysis of high precision, Low power current mode Sample 7
Hold circuit.
[email protected] +91-8130809758 www.siliconmentor.com
IEEE Projects
• Study of Sample & Hold Circuit for Analog to Digital conversion.
• Pseudo differential CMOS sample-and-hold circuit with low hold pedestal at 1.5-V 50-MHz .
• A single stage fully differential folded cascode amplifier using gain boosting technique at 90nm CMOS technology.
• Study and Performance Analysis of differential cascode amplifier.
• Realization of high performance D-flip flop design using MTCMOS technique through low power clocking .
• Design of Full Adder using 8t for ultra low power application
• Analysis of pre-capturing flip flop at 90 nm CMOS process technology for high speed and low power applications.
[email protected] +91-8130809758 www.siliconmentor.com
Projects Guidance Program
Silicon Mentor provide guidance to M.tech/PhD students in their final year project implementation.
Contact Us:www.siliconmentor.com+91-8130809758 [email protected]
