Latch-based Design
12
EE141 1 gital Integrated Circuits 2nd Timing Issues Latch-based Latch-based Design Design
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Latch-based Design. D. Q. Clk. T. Clk. t hold. D. t su. t c-q. Q. Register Parameters. Delays can be different for rising and falling data transitions. D. Q. Clk. T. Clk. PW m. t su. D. t hold. t d-q. t c-q. Q. Latch Parameters. - PowerPoint PPT Presentation
Transcript of Latch-based Design
EE1411
© Digital Integrated Circuits2nd Timing Issues
Latch-based Design Latch-based Design
EE1412
© Digital Integrated Circuits2nd Timing Issues
Register ParametersRegister ParametersD
Clk
Q
Delays can be different for rising and falling data transitions
D
Q
Clk
tc-q
thold
T
tsu
EE1413
© Digital Integrated Circuits2nd Timing Issues
Latch ParametersLatch Parameters D
Clk
Q
Delays can be different for rising and falling data transitions
D
Q
Clk
tc-q
thold
PWmtsu
td-q
T
EE1414
© Digital Integrated Circuits2nd Timing Issues
Latch timingLatch timing
D
Clk
Q
tD-Q
tClk-Q
• When data arrives to transparent latch- latch is a “soft” barrier
• When data arrives to closed latch - data has to be ‘re-launched’
EE1415
© Digital Integrated Circuits2nd Timing Issues
Flip-Flop – Based TimingFlip-Flop – Based Timing
Flip-flop
Logic
Flip-flop delay
Skew
Logic delay
TSU
TClk-Q
Representation after M. Horowitz, VLSI Circuits 1996.
EE1416
© Digital Integrated Circuits2nd Timing Issues
Timing ConstraintsTiming Constraints
R1
D QCombinational
LogicIn
CLK tCLK1
R2
D Q
tCLK2
tc qtc q, cdtsu, thold
tlogict
Minimum cycle time:Tclk tc-q + tsu + tlogic
Basic constraints without clock skew and jitter
Hold time constraint:t(c-q, cd) + t(logic, cd) thold
EE1417
© Digital Integrated Circuits2nd Timing Issues
Latch-Based TimingLatch-Based Timing
L1Latch
Logic
Logic
L2Latch
L1 latch
L2 latch
Skew
Can tolerate skew!
Longpath
Shortpath
Static logic
EE1418
© Digital Integrated Circuits2nd Timing Issues
Synchronous Pipelined DatapathSynchronous Pipelined Datapath
In
tpd,reg tpd1
D
R1
Q
CLK
LogicBlock #1
tpd2
D
R2
QLogic
Block #2
tpd3
D
R3
Q D
R4
Q LogicBlock #3
TCLK
CLK
TCLK
Block #1
Block #2
• Register based pipeline
The computation between the registers must be completed within Tclk
EE1419
© Digital Integrated Circuits2nd Timing Issues
Latch-Based DesignLatch-Based Design
L1Latch
Logic
Logic
L2Latch
L1 latch is transparentwhen = 0
L2 latch is transparent when = 1
EE14110
© Digital Integrated Circuits2nd Timing Issues
Register-based vs Latch-based PipelineRegister-based vs Latch-based Pipeline• Register-based: using edge triggered registers
CombinationalLogic
R1 R2Cin Cout Out
In
CLK
• Latch-based: using level transparent latches- break combinational logic in two blocks- replace register by two lathes and move second latch between the blocks
Clk ClkClk
Logic Block 1
Logic Block 2
In OutL1a L1b L2a
EE14111
© Digital Integrated Circuits2nd Timing Issues
Latch-based Pipeline designLatch-based Pipeline design
CLK1
CLK2
TCLK
Nominal computation:
Computation in each block is nominally performed in phase CLK=0 (block A computes when CLK1= 0, block B computes when CLK2=0)
The entire computation of d must be ready by edge 4 => Delay =1.5 Tclk
tpd,AIn must be ready prior to CLK1=0
a valid
tpd,Bc valid
d ready
tsu+ tDQ
CLB_A CLB_BInput
b ready
QDIn CLB_A QD QD
CLK1
L1 L2 L1
CLK2 CLK1
CLB_Btpd,A tpd,Ba b c d e
EE14112
© Digital Integrated Circuits2nd Timing Issues
Slack-borrowing Slack-borrowing
CLK1
CLK2
TCLK
tpd,A
a valid
tDQ tpd,B
b valid d valid
tDQ
e valid
slack passed to next stage
= slackc valid
CLB_A computes CLB_B computes
Actual computation can start earlier, when CLK=1, as long as data is available and stable (e.g. block A does not have to wait for CLK1 to be 0)
QDIn CLB_A QD QD
CLK1
L1 L2 L1
CLK2 CLK1
CLB_Btpd,A tpd,Ba b c d e
