Laser Processing of Si-TFT’s on Plastic:Technology and Lessons from FlexICs

Michael Thompson – MS&ECornell University

Flexible Electronics Course LectureApril 4, 2006

Applications for Flexible Electronics

Memory

IntegratedElectronics

OpticalNetwork

SmartCard

HDI

Display

Imaging Solid StateLighting

TFT Active Matrix on Polymer

Faster speedBetter resolutionLower power consumptionIntegrated drivers

Lower capital investmentLower product costThinnerLighterStronger

Poly-Si

Plastic

+

TFT on Plastics Enables “System LCD”

HIGH-QUALITY ITOBetter image quality

ACTIVE-MATRIX Poly-SiVideo color display

INTEGRATED DRIVERSSmall foot print

An Example

Flexible Backplane

FlexICs unique technology opensthe door to next generation displays,perfectly suited for µPDAs :

• Light and thin, yet sturdy and flexible• Compatible with all display media

technologies (LCDs, Bi-LCDs, OLEDs,Electronic Ink, etc.)

Technology Overview• Display electronics on

flexible plasticsubstrates– Thin Film Transistors

(TFT’s) switch eachpixel ON/OFF

– Integrate driver circuits(requires highperformance TFT’s)

• TFT structure– Materials: silicon,

metals, glass (SiO2)layers

– Simpler version ofintegrated circuit chips

Aluminum

poly Silicon

Pixel

Flex Stainless Steel (E-Ink)

• 1.6” diagonal• 80 ppi (100x80)• 0.30mm thickness

Flex Stainless Steel Prototypes

• 1.6” diagonal• 80 ppi (100x80)• 0.30mm thickness

Other Flexible Prototypes With E Ink

• 20 ppi backplanea-Si on Polyimide(roll-to-roll) (2001)

• Printed organicTFT on plasticsubstrate incollaboration withLucent (2001)

• Ink on cotton cloth:direct-drive segmentedbackplane

• Ink on plain paper:direct drivebackplane with mask

Organic TFTs• Best OTFT mobility 3 – 10x > a-Si:H• Stability, reproducibility, uniformity, compatibility

questions remain• Opportunity: molecular structure engineering for

improved transport and low-temperature solutionprocessing

Si

Si

Solutionprocessable

TIPS-pentacene

Key Drivers• Integration Level

– Incorporation of drive electronics with display backplanes– Active sensing and control

• Flexibility– Conformal applications

• X-ray sensors• Wrap around displays

• Mechanical robustness

• Cost– Opportunity to open new manufacturing methods– Plate-to-plate electronics– Roll-to-roll manufacturing

Manufacturing Plan

Pilot Production(wafer based)

Cost savings!

Existing technologies –time to market

Cap Ex est.: 1:3 ratio

Mfg Cost est.: 1: 2.7 ratio

Roll to Roll

Plate to Plate Plate to Plate

Roll to Roll

Solar Cells on Plastic Rolls (Sanyo)

Competition: Continued growing AMLCD glass sizes

Corning Family Volume by Generation

0

100

200

300

400

500

600

700

2002 2003 2004 2005 2006 2007

MM

sq.ft.

Gen8Gen7Gen6

Gen5

Gen 3-4

100 MM ft2 shipped in 2002

Flexible glass substrates

Flexible glass substrates

• Durable for military applications

• Effective barrier to air and moisture forOLEDs

• Corning has patented hermetic sealingmethod

• Low-cost manufacturing process

• Researching polymer coatings

SiliconMetal

Lamp

Photomask

Supply Roll Take-Up Roll

Supply Roll Take-Up Roll

Etch Bath

Transfer Rolls

TransferRolls

Thin Film Deposition& Laser Processing Photolithography

Wet ChemicalEtching & Cleaning

SiO2CoolingDrumLaser

Take-UpRoll

SupplyRoll

Roll to Roll Manufacturing

Large Roll Coater Equipment

Small Roll Equipment

Roll-to-roll Manufacturability Studies

• Initial development ondeposition and laserprocessing

• Ongoing discussions withlithography toolmanufacturers

0.1

1.0

0 20 40 60 80 100

length (mm)

Yie

ld

1 um

2 um

4 um

10 um

20 um

Expon. (2 um)

Expon. (1 um)

Expon. (4 um)

Expon. (10 um)

Expon. (20 um)

Characterization of defectgeneration in roll-to-roll webhandling

Why Laser-Crystallized a-Si?

• TFTs: essential devices in active matrix liquid crystaldisplays.

• a-Si:H TFTs: low performance (µ ≤ 1 cm2/Vs ).• poly-Si: higher mobilities (up to 500 cm2/Vs ); higher

aperture ratios (brighter), lower consumption, fasterresponse times.

• Poly-Si TFTs enable integrated driver circuitry, OLED-displays.

• Laser-crystallization: compatible with low-cost glasssubstrates; low temperature process, spatially selective⇒ superior to solid phase crystallization.

Alternative TFT Technologies• Low / moderate performance on plastic

– Amorphous Si TFTs• Uniformity• Developed Technology

– Polymer / Small molecule organic TFTs• Potential low-cost processing / printed technology

• Substrate selection– Stainless steel foils– Ultra-thin glass

• Transfer technologies– SUFTLA thin-film transfer– Wafer scale exfoliation– Thin-film single-crystal platelets

• Other crystal techniques– Microcrystalline deposition (performance?)

Application driven requirements: Mobility• Electron/hole mobility: transit speed across device• Gate capacitance (dielectric thickness): carrier density in channel• Ultimate technology speed depends on mobility, gate capacitance, and

uniformity (to utilize both)

Yes400 - 600Driver electronics. TFT electronics(processors, memory)

Near single-crystalpoly-Si (e.g. SLS)

YesYes

No

Yes

No

No

Low Tcomp?

300 – 500?High resolution small displays (digitalcameras)

Continuous GrainSilicon (CGS)

0.5 - 1.0Mainstream TFT-LCD (laptops, PDA’s)Amorphous siliconResearch

LCD prototypes

Medium and high performance displays(laptops, digital cameras, OLED)

Microprocessors (pentium), microdisplays

Application

0.1 - 5Organics

10 - 100Poly-silicon(furnace annealed)

40 - 400Poly-silicon(laser annealed)

650 +Silicon CMOS

Mobility(cm2/V-s)Technology

Key challenge: Static SemiconductorProcessing Temperatures

Technology Process Temperatures Substrate Materials

ULSI (Pentium) > 1050 °C(oxidations, anneals, etc.)

Crystalline Silicon,Silicon on Insulator,

Quartz

TFT-LCD(LTPS)

poly-Si: 600 °C (furnace anneal)poly-Si: 425 °C (excimer laser)a-Si: 250 °C

Corning 1737, 7059display glass

TFT on Plastic 100-250 °C (poly-Si and a-Si) Polymers (polyester,

PES, kapton)

Current technologies

Almost arbitrary –plastic, glass, steel,silicon, quartz

High temperaturedisplay glass plates(e.g. Corning 1737)

Silicon wafers or fusedsilica (quartz)

CompatibleSubstrates

Sub 150oC to ~300oCdepending onsubstrate

Room temperaturecontact process

Poly-Si or metal gate,room temperature Almetallization

Sputter depositionand laser anneal

Laser anneal only –room temperature

Sub 100oC oxidedeposition

Ultra Low TProcess

350-400oC plasma orfurnace

UnnecessaryHydrogenPassivation

400oC contact sinterand H2 passivation

400oC Contact SinterContactAnneal

Aluminum, Tungsten,Chromium,Molybdenum, etc…

Poly-Si, Aluminum orCopper Metallization

Gate andMetallization

~400°C depositionplus thermal or laseranneal

Thermally Grown Poly-Si

Poly-Siprocess

~600°C furnace orlaser anneal

Dopant ActivationAnneal (900°C)

DopantActivation

300°C+ deposition(LPCVD or similar)

Thermal Furnace(1000°C)

GateOxidation

Typical LTPSProcess

ULSI Process

Technology Goals for poly-Si TFTs• Low temperature process

– Compatibility with transparent polymericsubstrates for display applications

– Maximum static process temperatures of~150oC

• High performance devices– Amorphous Si and organic TFT’s have

inadequate current (mobility <10 cm2/V-s)– Poly-Si or near single crystal (200 cm2/V-s)

required

• Critical front-end processing (FEP) challenges– Crystallization of poly-Si– Dopant activation– Low temperature gate dielectric

• Critical back-end processing (BEP) challenges– Contact sintering– Hydrogenation– Pixel module integration

Moistureabsorption

Polyethersulphone(PES) 230°C 230°C

Amber colorPolyetheretherketone (PEEK) 250°C 250°C

Opaque, poorsurface finishSteel 900 900°C°C

Temperature,moisture

absorptionPolyester (PET) 120 120°C°C

Temperature,moisture

absorptionPolyethylenenapth

alate (PEN) 150°C 150°C

Brittle,hazy/colored,

Polyetherimide(PEI) 200°C 200°C

Orange color,high moisture

absorptionPolyimide (Kapton) 275 275°C°C

PrimaryChallengesMaterial

MaxProcess

Temp

Key elements in the thin film TFT

Al Al

Barrier SiO2

Substrate (Plastic or otherwise)

• Passivation or barrier SiO2 layer– Structural and electrical limiter– Thermal expansion mismatch– Limits high-T processes even on high-T compatible substrates

• Channel and Source/Drain semiconductor– High performance by laser crystallization

• Gate dielectric– Coupled with channel properties determines transconductance

Source/drain (doped)Gate dielectricGate metal

(self-aligned?)

Active Matrix OLED Pixel Cross-Section

• TFT provides correct current level (~10 µA) to OLED for desired intensity.

SiO2

Al AlAl

AlSiO2

SiO2

Plastic Substrate

Barrier SiO2

Cathode

SiO2

SiO2

ITO OLED

Light isemittedthrough

substrate

Passivation Layer

SiO2

Plastic Substrate

Cur

rent

Flo

w

Phases of Silicon

Crystalline PhaseLong Range Order

Semiconducting

Free

Ene

rgy

Temperature

Amorphous PhaseShort Range Order

similar to crystallineSemiconducting

Liquid PhaseVery limited orderMetallic bonding

Crystal

Amorphous

Liquid

TmcTm

a

Formation of High Quality Si at 150oC• Poly-Si deposition at moderate temperatures

– LPCVD requires ~550-600oC• Solid-state crystallization

– Requires ~500oC– Reduced temperature by Ni-induced epitaxy to ~400oC

• a-Si deposited at low temperature:– PECVD: high hydrogen content (up to 15 vol.%)– Sputtering: gas content variable– Low-pressure sputter to minimize hydrogen content

• Excimer laser crystallization– a-Si converted to poly-Si– hydrogen concentration (if present) reduced to <2%– silicon can be heavily doped– underlying substrate thermally isolated and not affected

• Minimal equivalent thermal budget• Thermal barrier “delays” heat load so plastic undamaged

Laser Processing: Derived from VLSI processing

Optics

Silicon

Laser

S/D Annealing TimesFurnace – 30-180 minutes

1960-1985RTA – 5-120 secs

1985-2000Spike – 0.01-3 secs

2000-2002

LTP30 ns-1 µs

Solid-state annealLSA

10 µs-1ms

Liquid-state anneal

liquid Si

Basic mechanism of laser crystallization

plastic

SiO2

a-Si / Si:H

Pulsed Laser exposure(excimer or other laser)

SiO2

Melting of a-Si

Full melt at 400 mJ/cm2 for 100 nm film

df=30-300 nm

plastic

SiO2

poly-Si

Solidification

time

mel

t dep

th

150 ns35 ns pulse

100 nm

λ=308 or 532 nm

plastic

τ=35 ns

Laser crystallization: ultrafast process, non-equilibrium phase transitions

XTEMS of LTP Junctions

Interface

Interface

FluenceNo Melt Partial Melt Full Melt

Over Melt Full MeltFull Melt

Metastable dopant activation – abrupt junctions

• More abrupt than as-implanted

• No dopant loss due toLTP

1.E+16

1.E+17

1.E+18

1.E+19

1.E+20

1.E+21

1.E+22

0 25 50 75 100 125

Depth (nm)

Bo

ron

Co

nc.

(cm

-3)

as implanted

0.16J/cm2

0.20J/cm2

0.26J/cm2

0.36J/cm2

0.38J/cm2

0.40J/cm2

0.44J/cm2

Laser Doping Apparatus

HeNe Laser633nm

Gas Cell with Wafer

Monitor

Fast Digitizing Oscilloscope

X-Y Stage

CCD Camera

Fiber Optic CouplerIR Laser

Computer

308nm XeCl Excimer Laser

OpticsPIN Diode

308 nm 532 nm 1064 nm

Laser wavelength choices

Challenges – Poly Si Formation• Excimer Laser Annealing

converts a-Si film to poly-Si– 30ns XeCl (308nm) pulse

absorbed in 50nm Si film– Similar to standard LTPS– Produces large grains for

high performance TFT’s

• SiO2 buffer layer trapsheat in silicon layer– Plastic is kept below 250ºC– Plastic substrate is not

damaged or deformed

LaserPulse

SiO2

polyester

35ns FWHM Excimer Laser Pulse

Si

In situ Laser Process Control

During Laser Pulse

Reflected Intensity

~ 70%

Penetration Depth ­10nm

Plastic

Molten Si

SiO2

a-Si:H

Dete

ctor

Dete

ctor

XeCl (λ=308nm,

35ns FWHM )

Transmitted Intensity < 5%

Before Laser Pulse

Plastic

HeNe laser (λ=632.8nm)

ReflectedIntensity

15-70 %

IR Laser(λ = 1.5µm)

Dete

ctor

Dete

ctor

SiO2

a-Si:H

Transmitted Intensity ~ 60%

Optical Reflectance on Si

•Temperature effects in c-Sicreate heat bump below melt

•Detect melt threshold frommultiple reflectance traces

•Calibrate laser energy usingtheoretical value ~600mJ/cm2

SOI(SIMOX) Devices (II)

0.98 m/s

4.83 m/s

0 100 200 300 400 500 600

0

1.0

Time (ns)

Tran

smis

sion

(nor

m.)

950 mJ/cm2

735530

425

220

340

Laser Process: IR Diagnostic

Silic

on c

ryst

alliz

esSilicon melts

Silicon is molten

Silicon “melt duration”

Mel

t Dep

th (Å

)

Melt Duration (ns)

1000Å Si / SiO2 / PET

0 50 100 150 200 250

1000

800

600

400

200

0

Laser Process Crystallization Control

90 ns

620 Å

Controlling Performance - Nucleation• Performance determined first by

grain structure in crystallized Si• Critical Laser Fluence: Full Melt

Threshold (FMT)– Fluence required to completely melt

Si film– Grain structure, mobility, roughness

all correlated to laser fluence• Irradiate Above FMT

– Homogeneous Nucleation– Small uniform grains (40-50 nm)

(µ ~ 50 cm2/V-s)• At/Near FMT:

– Few seeds, large (5 µm) grains– High performance, lower uniformity

(µ ~ 400 cm2/V-s)• SLS: grains >>10 µm

– highest performance– (µ > 400 cm2/V-s)

SiO2 substrate

Si nucleiliquid Si

SiO2 substrate

Si nucleiliquid Si

Laser Fluence

Gra

in s

ize

/ Mob

ility

Full Melt Threshold

Mel

t Th

resh

old

Growth regimes in laser crystallization

amorphous Si

SiO2

liquid Si

fine grain Si (EC)

Partial meltNear full melt

Full melt

Nucleation event triggers fastmelt/crystallization front

Vertical ExplosiveCrystallize

residual solid Si

Lateral growth fromunmelted seeds ⇒large grains

Super Lateral Growth Homogeneous Nucleation

Undercooling ⇒ solid Siclusters form and grow

Larger grains (VC)

SiO2 substrate

Si nucleiliquid Si

SiO2 substrate

Si nucleiliquid Si

interfacevelocity

polycrystal amorphousliquidthermal barrier oxide

heat sink (control surface)

vcl val

wh

tem

pera

ture

Tma

TmcTcl

Tal

position

energyreleased energy

absorbed

heat flowΣ K(∂T/∂s) = v ΔHac

Explosive crystallization front

Plan view brightfield TEM 200 nm1 µmAFM 60 nm Z-scale

20 µmDark Field Optical Micrograph

•Extendedcolumnar grain –nearly singlecrystal for asmuch as a mmgrowth

• Nearly constantvelocity incolumnar regime

• Surface featuresroughly parallelto crystallizationdirection

High velocity regime – low heat loss

Evolution of grain structure with fluence

175 mJ/cm2

0 0.5 1 1.5 2 µm 0 2.5 5 7.5 10 µm

b

0 0.5 1 1.5 2 µm

ca310 mJ/cm2 350 mJ/cm2

Partial melt ⇒explosive crystallization

Near full melt ⇒ superlateral growth

Full melt ⇒ homogeneousnucleation and growth

50 nm a-Si:H film,XeCl irradiation

Atomic force microscopy

Super lateral growth: large (≥ 3 µm) grains ⇒ high device performanceBUT wide grain size distribution ⇒ non-uniformity in device characteristicsalso: narrow processing window

Grain design – application optimized• “Uniformity” key requirement

– “backplane” pixels for displays– Mobilities in ~10 cm2/V-s adequate– Matching required to avoid visual effect (or calibration)– Leakage often greater driver than transconductance (on/off)– above FMT for uniform distributions … uniformly bad

• Issue: Above FMT exhibits poor behavior on deposited barrieroxides. Need understanding/development of new barriers

• “Speed” key requirement– Driver circuitry / logic– Maximize mobility, but design constrained by uniformity– controlled drive up the mobility curve

• Issue: Laser control uniformity. Need <1% pulse-pulse stability andareal uniformity

• Die-by-die versus line scan options versus active area irradiation

150oC TFT on Plastic Process Steps 1. deposit compliance layer and thermal

isolation oxide2. deposit a-Si3. crystallize a-Si (excimer laser)4. deposit gate oxide5. deposit gate electrode

6. pattern gate (mask # 1)7. dope source/drain

• Implant + laser anneal• In-situ doping + laser anneal

8. pattern Si device regions (mask # 2)

9. deposit contact isolation oxide10. pattern & etch contacts (mask # 3)11. deposit and pattern metal (mask # 4)

12. Low-T ITO deposition and patterning

doped polysiliconPlastic Substrate

Compliance & Thermal Barrier

Metal or poly-Si

poly-SiGate SiO2

542,31

doped polysiliconPlastic Substrate

Barriers

M

Sin+ Si n+ Si

6

7,8

doped polysiliconPlastic Substrate

Barriers

SiO2

SiO2

Al M

SiAl

SiO2

11

9,10 n+ Si n+ Si

ITO 12

Test pattern

Each die contains TFTswith different sizes

Display

Gate Voltage

log Drain-SourceCurrent

Sub-thresholdSlope

(volts/decade)

Gate Voltage

Drain-SourceCurrent(to OLED)

Mobility

ThresholdVoltage

TFT Performance Metrics• Mobility: high current capability

(OLED display brightness andfast driver circuits)

• Threshold voltage control• Sub-threshold slope (steep on-

off transition)• Device uniformity

doped polysiliconPlastic Substrate

SiO2

SiO2

SiO2

Al G

SiAl

SiO2

GATE DRAINSOURCE

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

160.0

0 5 10 15 20VDS (Volts)

I DS (µ

A)

VG = 20.0V

VG = 17.5V

VG = 15.0V

VG = 12.5V

Typical TFT on Plastic Performance

• 100ºC maximum process temperature

10 -11

10 -10

10 -9

10 -8

10 -7

10 -6

10 -5

10 -4

10 -3

-10 0 10 20 30 40

I DS (A

mps

)

VGS (Volts)

VDS =1.0V

VDS =10.0V

W/L = 100/50 µm

µn = 44 cm2/V-secS = 1.7 V/decade

“High-performance” TFT results• NMOS TFT performance:

– Mobility > 250 cm2/V-s– Threshold voltage ~ 5 V– Sub-threshold swing:

~ 0.5 V / decade

• PMOS TFT performance:– Mobility ~ 125 cm2/V-s– Threshold ~ -5.5 V– Sub-threshold swing

~ 1.2 V / decade

-5 0 5 10

Gate Voltage VG (volts)

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

DrainCurrentIDS(amperes)

VDS

= 5.0 V

-5 0 5 10

Gate Voltage VG (volts)

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

DrainCurrentIDS(amperes)

-5 0 5 10

Gate Voltage VG (volts)

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

DrainCurrentIDS(amperes)

VDS

= 5.0 V

W/L = 20/10

Results (PECVD Si from AKT)

1.E-02

1.E-01

1.E+00

1.E+01

1.E+02

1.E+03

0 20 40 60 80 100 120 140 160 180 200 220

Gate Width (um)

Mob

ilit

y (

cm2/V

-s) poly-Si

(>FMT)

a-Si

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

0 20 40 60 80 100 120 140 160 180 200 220

Gate Width (um)

ON

Cu

rren

t (A

)

poly-Si

(>FMT)

a-Si

1.E-12

1.E-11

1.E-10

0 20 40 60 80 100 120 140 160 180 200 220

Gate Width (um)

OF

F C

urren

t (A

)

poly-Si

(>FMT)

a-Si

0.E+00

1.E+00

2.E+00

3.E+00

4.E+00

5.E+00

6.E+00

0 20 40 60 80 100 120 140 160 180 200 220

Gate Width (um)

Th

resh

old

Volt

age (

V)

poly-Si

(>FMT)

a-Si

10-14

10-13

10-12

10-11

10-10

10-9

10-8

Minimum OFF Current (Amperes)

0

5

10

15

20

DieCount

CTR=-11.2 FWHM=0.572 (S=0.343) AVG=-11.2 MED=-11.2 STD=0.65 X3S=1.99

tft10b10sw.gate.1

TFT10B10SW SW 10/10

akt6-4/annealed

TFTGATE (VDS=5.00)

3:47 PM 5/3/99

10-4

10-3

Maximum ON Current (Amperes)

0

2

4

6

8

10

12

14

DieCount

CTR=-3.5 FWHM=0.128 (S=0.0771) AVG=-3.49 MED=-3.49 STD=0.0593 X3S=0.149

tft10b10ne.gate.1

TFT10B10NE NE 10/10

akt6-6/annealed

TFTGATE (VDS=5.00)

3:36 PM 5/4/990 50 100 150 200 250 300

Mobility (cm2/V-s)

0

5

10

15

20

25

DieCount

CTR=181 FWHM=39.5 (S=23.7) AVG=182 MED=183 STD=18.4 X3S=42.1

tft10b10ne.gate.1

TFT10B10NE NE 10/10

akt6-6/annealed

TFTGATE (VDS=5.00)

3:36 PM 5/4/99

-6 -4 -2 0 2 4 6

Threshold Voltage [NORM] (V)

0

10

20

30

40

50

60

DieCount

CTR=0.954 FWHM=1.84 (S=1.1) AVG=0.959 MED=1.07 STD=0.845 X3S=3.23

tft10b10ne.gate.1

TFT10B10NE NE 10/10

akt6-6/annealed

TFTGATE (VDS=5.00)

3:36 PM 5/4/99

Distribution of TFT parameters (W/L = 10/10)

Critical Process Steps (beyond Si)• Barrier Oxide layer

– Passivation between polymer (or other substrate) and poly-Si– Transition of thermal properties from high-T (laser) to substrate– Compatibilization of thermal expansion properties

• Si film– Grain boundary reduction – near single crystal grains– Control of grain size / distribution – potentially area dependent– Surface roughness– Linking impurity doping with laser processing

• Low temperature gate oxide– Interface quality establishes channel mobility (with grain size)– Trapped and mobile charge control– Conformable – thin film or high-K to increase transconductance

• Post-device annealing– Hydrogen passivation: Currently requires ~350OC and high T substrates

• Lithography– Run-out– Dimensional changes (anisotropic) increase required gate-S/D overlap and

parasitics

Low Temperature Gate Oxide (SiO2)

• Critical for high performance devices– Defects: bulk oxide, mobile ions, interface states

• reduce mobility• increase threshold voltage• increase sub-threshold slope (turn-on)

• Deposition Techniques– PECVD

• Silane decomposition• TEOS

– ECR (electron cyclotron resonance) PECVD– Reactive sputtering

FlexICs: Ultra low temperature gate dielectric

--Thermal Oxide (1000 oC)--100°C FlexICs Oxide

• Most low temperature (< 200ºC) oxides⇒ defects– Porous films with trapped gases in SiO2

network– Charged defects in bulk oxide material– High interface trap densities⇒ Reduced device performance

• Low Temperature SiO2 DepositionTechniques– PECVD: silane, disilane, TEOS– Electron cyclotron resonance (ECR) CVD– Reactive sputtering in O2 and O3– FlexICs proprietary technology⇒ Highest performance ≤100º C

Direct Dopant Deposition and Laser Mixing

Creates Low Resistivity Si - Few Laser Pulses• control dopant concentration with deposition duration• control dopant depth with laser energy fluence• low sheet resistance after only one laser pulse (200 Ω/square)• No damage to substrates

SiO2

plastic

Excimer Laser Pulse

Dopant Layer

Si

Hydrogen passivation• High temperature substrates

– 350oC polyimide can accept direct hydrogen plasma treatment

• Sacrificial hydrogen doping sources– Si3N4:H source layer + laser annealing

• Transient high temperature anneals– Millisecond regime still minimizing substrate damage– Laser Spike Annealing

Major “Commercialization” Issues• Processes all developed as “wafer” scale operations

• Scaleup issues to either plate-to-plate or roll to roll– Wafer lamination / handling– Area scaling deposition techniques

• Barrier deposition – continuously varied stoichiometry / rates• Low-pressure Si sputtering for low H content• Gate dielectric deposition – rates at 100oC

– Laser utilization• Too many laser steps cost issues• Stability and control over large areas / uniformities

• Cost structure– Not significantly different than existing semiconductor processes

Significant new directions• Direct printing methods

– Additive versus subtractive

• “Slurry” dispersions– Si micro-crystallites dispersed in ink-jet printable dispersions– Formed as platelets for self-assembly with um grain sizes– Laser anneal at low fluence to address grain boundary

• SLS – selective lateral solidification– Localized annealing for device structures only (% of area)– Grain enhancement to single-grain performance

• Oxide semiconductors– ZnO and similar intrinsically stable materials

Technical Summary• Poly-Si TFTs on low-temperature flexible substrates will

have applications in mid-performance systems• Pulsed laser processing provides route to moderate

grain size with minimal substrate degradation• Control of laser conditions establishes regimes for high

performance or high uniformity

• Critical steps remain– Control of laser process characteristics– Continued development of low-T gate oxides, especially high-K– Hydrogen passivation– Lithography control for device design (size and overlaps)

Acknowledgements• FlexICs / Livermore teams

– Pat Smith– Paul Wickboldt– Paul Carey– Tom Sigmon

• Cornell Students– Wonsuk Chung– Scott Stiffler– Kevin Dezfulian– Connie Lew– Shenzhi Yang

FlexICS: The Business Side

Experiences, Successes and LessonsLearned

Origins of FlexICs• DARPA funded flexible electronics project at Lawrence

Livermore National Labs 1997-1999– Paul Carey (Stanford Ph.D)– Pat Smith (Harvard Ph.D)– Paul Wickboldt (Harvard Ph.D / Princeton Postdoc)– Mike Thompson (sabbatical)

• Technology proven on small scale (4” wafers) with SDIfunded equipment

• Drives to “leave the lab”– Control and large scale integration limited by equipment set– Extremely high cost of doing business in National Labs (300%

overhead)– Everyone was making tons of money on telecom and internet

startups– Desire to “prove” the technology for commercialization

Strength of the Activity• Key patents filed at Lawrence Livermore on

– Sub-150oC processing of Si on flexible substrates– Laser assisted doping at low temperate

• Negotiated licensing fees with Livermore for “co-exclusive” access to the patents and any subsequentpatents– Government agency forced to provide equal terms to a

competitive operation

• Knowledge base– Only group at the time with ability to fully integrate the process

• In retrospect – weak IP position

Initial Funding Efforts• Business Plan

– $5-8M to prove technology outside the lab– Acquire critical equipment (deposition / oxide)– Continue working within lab / leveraged by Stanford/CNF

• Angel Investors – seed money in $100-$300K range– Inadequate to make any significant progress

• Venture Capital groups– Appropriate level, but no “track record” by management team– Time horizon / investment level biased by dot-coms and telecoms

• Corporate Venture groups– Strategic partners with vested interest in the technology– Dupont / Intel / Bose / E-Ink / Opticom

Fortuitous events• Substantial interest from Dupont for strategic investment

– Negotiation points were associated with patent rights and licensingconditions

• Interest from single corporate site brought additional interest fromVC groups– Draper Fisher Jurvitson– Intel Capital

• Snowball effect– Dot-coms were on the brink of collapsing.– VCs looking for more “hard” investments with big payoff– VCs pushed to take lead and complete the financing

• 1st round $8M for operations

Management• Advantages of VC funding

– Access to key personal

• Identified Magnus Ryde as potential CEO– KLA Tencor (semiconductor equipment manufacturer)– President TSMC USA – largest semiconductor manufacturer– Limited partner in the VC – Palo Alto Investments

• CEO identified and recruited equally strongmanufacturing, marketing and sales– Heiner Eichmuller – Siemans solar for plant/facility development– Shyam Dujari – Marketing with knowledge of Asian manufacturer– Len Marsh - Financing

Early Optimism Goes Overboard• Expectation of rapid manufacturing transition• Reality:

– Many issues in the transfer of processes from lab to facility– Tool development poor choice of resource– Designed as a scaled up lab / not a manufacturing operation– Process poorly defined – depend on “individual” expertise

• Marketing and management proceed toward large scaleoperation– Raise additional capital for completion of move out of lab

facilities to fully operational clean room– Second round financing to $25M

Marketing Reality• Interest in flexible substrates was extensive but …

– Only when cost competitive with existing glass based panels– Expectation of dramatic cost advantage– Required equivalent performance on early learning curve

• Develop new markets– Extensive opportunities in the telecommunication arena– New patents with joint partners on thermal modulated optical

switching / active control– Smart cards applications– Memory applications

• No new markets could drive the development of theentire activity – had to rely on displays

Manufacturing Reality• Too late recognized inability to manufacture in the limited

facilities• Investment requirement for panel-to-panel operation

– $100M equipment in “depreciated” arena– Develop strategic partnerships with Taiwan / Japan– Issues with Govt. IP

• Level of investment beyond VC – corporate time scaleslong– Funding limited – attempt to conserve to partnership

Technology Reality• Success

– TFTs were ultimately fabricated on 6” wafers with necessaryperformance levels for OLED displays

– Demonstrations with Uniax and Kodak– Yield and uniformity still required improvement

• OLED integration– Barrier layer never materialized– Market for OLED truly flexible displays disappeared

Key Stumbles• Attempting too large of a technical task on limited

funding– Process development– Key hardware development– Integration with startup equivalents

• Leaving the lab environment too soon.– Process freeze was really necessary before moving to

manufacturing

• Unrealistic expectations of capabilities in given lab

• Personnel issues