Lag controller design

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Lag controller design • It has “destabilizing” effect (lag) • Not used for improving M P , t r , … • Use it to improve e ss • Use it when R.L. of G(s) go through the desired region but e ss is too large. p z p s z s K s C ,

description

Lag controller design. It has “destabilizing” effect (lag) Not used for improving M P , t r , … Use it to improve e ss Use it when R.L. of G ( s ) go through the desired region but e ss is too large. Design steps. From specs, draw desired pole region - PowerPoint PPT Presentation

Transcript of Lag controller design

Page 1: Lag controller design

Lag controller design

• It has “destabilizing” effect (lag)

• Not used for improving MP, tr, …

• Use it to improve ess

• Use it when R.L. of G(s) go through the desired region but ess is too large.

pzps

zsKsC

,

Page 2: Lag controller design

Design steps

1. From specs, draw desired pole region

2. Draw R.L. for G(s). (it goes through )

3. Select pd on R.L. & in region

4. Get

5. With that K, compute error constant(Kp, Kv, Ka) from KG(s) (call it Kva)

6. From specs, compute Kvd

dpGK

1

Page 3: Lag controller design

7. If Kva > Kvd , done

else: pick

8. Re-compute

9. Closed-loop simulation & tuning as necessary

20~5

Re dpz

vd

va

K

Kzp

dpdp

zdp pGK

1

Page 4: Lag controller design

Example:

Want:

Solution:

%161 PM

sec5,sec202 rs tt

0step to3 sse2.0ramp to sse

5.0%16 PM

36.0sec5 nrt

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2.0sec20 st

Draw region

Page 6: Lag controller design

• Draw R.L.

• Pick pd on R.L. & in Regionpick pd = – 0.35 + j0.5

• Since there is one in G(s)

86.01

211

ddd

d

ppp

pGK

s

1

0step to,1Type sse

vss K

e1

ramp to

Page 7: Lag controller design

2.0:Desired sse

52.0

1 vdK

:have What we ssKGK

sva

0lim

43.021

186.0lim

0

ssss

s

07.0

5

35.0RePick

dp

z

006.05

43.007.0 p

Page 8: Lag controller design

: compute-Re K

914.0

1

dpdp

zdp pGK

%28:Simulation PM

?,5 sr tt

20 toratio that reduce :Tune

%8then, PM

?,5 sr tt

Page 9: Lag controller design
Page 10: Lag controller design

A better tuning may be to go back and re-pick pd

Page 11: Lag controller design

• Lag control can improve ess, but cannot eliminate ess

• Use PI control to eliminate ess

• PI : s

sKK

sKKsC PI

IP

1

s

sK

s

zsK I

IP

1

P

I

K

Kz :where

zK

K

I

PI

1

Page 12: Lag controller design

• Only advantage of PI: remove ess

• It has destabilizing effectMay ↑ MP , ↑ ts , etc.

• “Sluggish” settling, just like Lag

• Needs trial and error tuning of Kp and KI

Page 13: Lag controller design

:design One

sGs

orig. toMultiply 1 1

sGs

1for design PD Do2

This way, just use your PDdesign program.

Page 14: Lag controller design

Second design:

1. Draw R.L. for G(s)

2. From specs, draw desired region

3. Pick pd on R.L. & in region

4. i. Choose

ii. Choose

5.

6. Simulate & tune

20~5

Re dpz

sGs

zssz

0s

lim s.t.

tsrequiremen meets sse

PI

pss

zsP KzKsG

K

d

,

1

Page 15: Lag controller design

Example:

Want:

Solution: Draw R.L.

0step to,%5 ssP eM

criticalnot speed

7.0%5 PM

cone 45

Page 16: Lag controller design
Page 17: Lag controller design

Clearly, R.L. pass through desired region.

Pick (right on boundary)

Choose

22 jpd

4.05

Re dp

z

4.0z

5.5

1

dpss

zsPsG

K

s

ssC

4.05.5

Page 18: Lag controller design

Step response: ess = 0

No MP (no overshoot)

fast rise to 0.85, then very sluggish to 1

Tune 1: KP ↑ to 2.5 KP 0,%5~4 ssP eM

sluggish but , fast sr tt

3

2,

3

Repick :2 Tune z

pz d

Page 19: Lag controller design

dpss

zsPsG

K

1

sluggish less

0PM

PP KK 5.1 Now

ssP eM no,%5

fastermuch st

smaller" dip"

Page 20: Lag controller design

best1

5.1

3

Re

dpss

zsP

d

sGK

pz

PP

d

KK

pz

5.25

Re

dpss

zsP

d

sGK

pz

15

Re

• None unique solution

• Design is a creative process based on science

Page 21: Lag controller design

Example:

Want:

%5PM

sec01.0rt

0.2acc to sse

aircraft2.361

4500

sssG

sec025.0st

Page 22: Lag controller design

Sol: G(s) is type 1Since we want finite ess to unit acc,

we need the compensated systemto be type 2C(s) needs to have in it

s

1

52.0

11lim 2

0s

ss

a esGsCsK

7.0%5 :From PM

45 of cone

Page 23: Lag controller design

1604

025.0 From s

s tt

18001.0

8.101.0 From nrt

160180 jpd

Page 24: Lag controller design

Draw R.L., it passes through the desired region.

Pick pd on R.L. & in Region

pick pd = – 180 + j160

Now choose z to meet Ka:

180240 dn p

2.361

4500lim 2

0

sss

zsKsK P

sa

5361

4500 zKP

Page 25: Lag controller design

Also:

dpss

zsPsG

K

1

4500

361

zp

pp

d

dd

dd pzp Re if

144500

361

dd pp

0287.04500

3615

PKz

Page 26: Lag controller design

Pick z = 0.03

Do step resp. of closed-loop:

Is it good enough?

s

ssC

03.014

025.00236.0 st

%5%84.3 PM

?01.00105.0 rt

2.01911.01

acc to a

ss Ke

Page 27: Lag controller design

14,03.0 PKz

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Design goal: 01.0rt025.0st

%5PM

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If tr = 0.0105 not satisfactorywe need to reduce tr by ≈ 5%

%5by ,1

nn

rt

2,but dPdn pKp

%5by increasetry PK

0232.0st

%49.4 :step Do PM

0099.0rt

sse