Lab4 Report Eel4712

Lab 4David Patchin

EEL4712 Section 1517Tuesday 12:50: 3/8/05

TA: Eric Siegel

ObjectiveThe objective of this lab is to design an 8-bit arithmetic logic unit (ALU) to study hierarchical design using VHDL

Pre-Lab

Section 1Enhance adder2lca from Lab 3 to produce adder2Xlca shown in Figure 1(a):• Bit-wise A AND B function to produce AND[1..0]• Bit-wise A OR B function to produce OR[1..0]• Bit-wise A XOR B function to produce XOR[1..0]

VHDL Code:--David Patchin--EEL 4712--Section: 1517--Lab 4 PreLab 1: 2-bit LCA Adder with eXtra functions

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY adder2Xlca ISPORT ( Cin : IN STD_LOGIC;

a, b : IN STD_LOGIC_VECTOR(1 DOWNTO 0);s, AandB, AorB, AxorB : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);Cout, BP, BG : OUT STD_LOGIC);

END adder2Xlca ;

ARCHITECTURE Xlca OF adder2Xlca ISSIGNAL P0, P1, G0, G1,C1 : STD_LOGIC;

BEGING0 <= a(0) AND b(0);P0 <= a(0) OR b(0);

G1 <= a(1) AND b(1);P1 <= a(1) OR b(1);

C1 <= G0 OR (P0 AND Cin);

s(0) <= a(0) XOR b(0) XOR Cin;s(1) <= a(1) XOR b(1) XOR C1;Cout <= G1 OR (G0 AND P1) OR (P1 AND P0 AND Cin);

BP <= P1 AND P0;BG <= G1 OR (G0 AND P1);

AandB(0) <= a(0) AND b(0);AandB(1) <= a(1) AND b(1);

AorB(0) <= a(0) OR b(0);AorB(1) <= a(1) OR b(1);

AxorB(0) <= a(0) XOR b(0);AxorB(1) <= a(1) XOR b(1);

END Xlca;

Functional Simulation

FIGURE 1a

DiscussionThis section of the lab boiled down to taking a previously

completed functional adder (from Lab 3) and adding a few extra functions to it. All that was done was adding a few behavioral VHDL lines of code to do a bit-wise AND, OR, and XOR functionality to the adder (the “eXtra” functions; as can be seen in the last 7 lines of the VHDL code). The simulation (Figure 1a) shows how both the proper adder results; including carry and propagation, and the eXtra functions are produced from the adder at the same time. This means that there is no meaningful delay added to the adder, which will help down the road when creating larger adders and ALU’s.

Section 2Design and simulate the 2-bit arithmetic logic unit (alu2lca) shown in Figure 1(a).• You are to specify the mux2_8to1 component yourself in VHDL.• For the mux2_2to1 component, you are to use an existing component (a_21mux) from the altera.maxplus2 library:• In your .vhd file that uses the a_21mux component, you need to include the library: LIBRARY altera ; USE altera.maxplus2.all;• To find the component definition for a_21mux, look into the following file:C:\Program Files\altera\quartus42\libraries\vhdl\altera\MAXPLUS2.VHD(assuming you installed your Quartus system in the directory named C:\Program Files\altera…)• For each explicit component you used in this design (like mux2_8to1 or any new component you choose to use),• Enter the design using behavioral VHDL.

VHDL Code (8to1 Mux)--David Patchin--EEL 4712--Section: 1517--Lab 4 PreLab 2: 8-1 mux to use as component for ALU


ENTITY mux2_8to1 ISPORT ( sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

i0, i1, i2, i3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);i4, i5, i6, i7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);f : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));

END mux2_8to1;

ARCHITECTURE mux OF mux2_8to1 IS

BEGIN

WITH sel SELECTf <= i0 WHEN "000",

i1 WHEN "001",i2 WHEN "010",i3 WHEN "011",i4 WHEN "100",i5 WHEN "101",i6 WHEN "110",i7 WHEN OTHERS;

END mux;

Function Simulation

Figure 2a

VHDL Code (LCA2Gen [from Lab 3])--David Patchin--EEL 4712--Section: 1517--Lab 3 PreLab 2: 2-bit LCA Generator


ENTITY lca2gen ISPORT ( c0 : IN STD_LOGIC;

p0, p1, g0, g1 : IN STD_LOGIC;c1, c2, BP, BG : OUT STD_LOGIC);

END lca2gen ;

ARCHITECTURE lcagen OF lca2gen ISBEGIN

c1 <= g0 OR (p0 AND c0);c2 <= g1 OR (p1 AND g0) OR (p0 AND p1 AND c0);

BG <= g1 OR (p1 AND g0) OR (p0 AND p1 AND c0);BP <= p1 AND p0;

END lcagen;

VHDL Code (Alu2lca)--David Patchin--EEL 4712--Section: 1517--Lab 4 PreLab 2: 2-bit ALU

LIBRARY ieee ;LIBRARY altera;USE ieee.std_logic_1164.all ;USE altera.maxplus2.all;

ENTITY alu2lca ISPORT ( Cin, SLin, SRin : IN STD_LOGIC;

sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);a, b : IN STD_LOGIC_VECTOR(1 DOWNTO 0);f : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);Cout, BP, BG, SLout, SRout: OUT STD_LOGIC);

END alu2lca ;

ARCHITECTURE alu OF alu2lca ISSIGNAL zero, AandB, AorB, AxorB : STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL AsllB, AsrlB, l, r, sum : STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL mux1 : STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL muxflag : STD_LOGIC;

COMPONENT a_21muxPORT ( s: in STD_LOGIC;

a: in STD_LOGIC;b: in STD_LOGIC;y: out STD_LOGIC);

END COMPONENT;

COMPONENT mux2_8to1PORT ( sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);

i0, i1, i2, i3 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);i4, i5, i6, i7 : IN STD_LOGIC_VECTOR(1 DOWNTO 0);f : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));

END COMPONENT;

COMPONENT adder2Xlca PORT ( Cin : IN STD_LOGIC;

a, b : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

s, AandB, AorB, AxorB : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);Cout, BP, BG : OUT STD_LOGIC);

END COMPONENT;

BEGINzero <= "00";

--SRR OperationSRout <= a(0);r(0) <= a(1);r(1) <= SRin;

--SLL operationSLout <= a(1);l(1) <= a(0);l(0) <= SLin;

muxflag <= sel(2) AND sel(1) AND sel(0);

--2to1 MUX STAGEstage1a: a_21mux PORT MAP(s=>muxflag, b=>b(0), a=>not(b(0)), y=>mux1(0));stage1b: a_21mux PORT MAP(s=>muxflag, b=>b(1), a=>not(b(1)), y=>mux1(1));

--ALU Stagestage2: adder2Xlca PORT MAP(Cin=>Cin, a=>a, b=>mux1, s=>sum,BG=>BG, BP=>BP, Cout=>Cout, AandB=>AandB, AorB=>AorB, AxorB=>AxorB);

--8to1 MUX Stagestage3: mux2_8to1 PORT MAP(sel=>sel, i0=>zero, i1=>AandB, i2=>AorB,i3=>AxorB, i4=>l, i5=>r, i6=>sum, i7=>sum, f=>f);

end alu;

Functional Simulation

Figure 2b

DiscussionThe first component created for the new 2-bit ALU was a 2-bit 8-

to-1 MUX (see VHDL code). This MUX will allow for multiple functions to be produced at the same time and for the user, or controller, the ability to select which function will be outputted from the ALU. Figure 2a shows how each input is propagated to the output when its specific channel has been specified. This will allow in an increase in performance, because all of the operations in the ALU will be done at the same time.

As seen in Figure 2b, the ALU also provides the shift left overflow as well as the shift right overflow. This will be very important later on when larger ALU’s will be constructed. These outputs can be connected

to other ALU’s or LCA generators to create a larger ALU with improved performance.

Section 3The block diagram of the 8-bit ALU (alu8lca) is shown in Figure 1(b). Alu8lca can perform one of 8 functions as selected by SEL[2..0]. These 8 functions are defined in the table shown in Figure 1(c). It also provides block generate (BG) and block propagate (BP) signals to support look ahead carry adder operations.• alu8lca has a “3-level” architecture. The “leaf” level consists of four 2-bitALUs (alu2lca). The other two levels consist of the LCA generator (lca2gen) designed in Lab 3.• Neatly draw a detailed circuit diagram by hand or as a .bdf for alu8lca, showing all the connectionsbetween the alu2lca and lca2gen components. Also, if necessary, add any components or logic toimplement alu8lca.• Enter the design of the 8-bit ALU using structural VHDL (PORT MAP statements). Again, tominimize errors, use “named” association for the PORT MAP parameters instead of “positional”association. Place the function table from Figure 1(c) in the VHDL file as a comment.• Perform a functional simulation using the appropriate test vectors. Capture the test vectors in a“.tbl” file for use in the lab report. (Save your simulation file “Save As” and choose “Save as type”to be Vector Table Output File (*.tbl).)

VHDL Code (alu8lca)--David Patchin--EEL 4712--Section: 1517--Lab 4 PreLab 3: 8-bit ALU


ENTITY alu8lca ISPORT ( Cin, SLin, SRin : IN STD_LOGIC;

sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);a, b : IN STD_LOGIC_VECTOR(7 DOWNTO 0);f : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);Cout, BP, BG, SLout, SRout: OUT STD_LOGIC);

END alu8lca ;

ARCHITECTURE alu OF alu8lca ISSIGNAL xBP, xBG, xCout, xSL, xSR : STD_LOGIC_VECTOR(3 DOWNTO 0);SIGNAL xxBP, xxBG, xxCout : STD_LOGIC_VECTOR(1 DOWNTO 0);SIGNAL xxxCout : STD_LOGIC_VECTOR(2 DOWNTO 1);

COMPONENT alu2lcaPORT ( Cin, SLin, SRin : IN STD_LOGIC;

sel : IN STD_LOGIC_VECTOR(2 DOWNTO 0);a, b : IN STD_LOGIC_VECTOR(1 DOWNTO 0);f : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);Cout, BP, BG, SLout, SRout : OUT STD_LOGIC);

END COMPONENT ;

COMPONENT lca2genPORT ( c0 : IN STD_LOGIC;

p0, p1, g0, g1 : IN STD_LOGIC;

c1, c2, BP, BG : OUT STD_LOGIC);END COMPONENT ;

BEGIN

---------------------------------------------- SEL FUNCTION-- 000 Zero Function-- 001 Bit-wise AND-- 010 Bit-wise OR-- 011 Bit-wise XOR-- 100 SLL-- 101 SRL-- 110 Addition-- 111 Subtraction--------------------------------------------

stage0a: alu2lca PORT MAP(Cin=>Cin, SLin=>SLin, SRin=>xSR(0), sel=>sel, a=>a(1 DOWNTO 0),

b=>b(1 DOWNTO 0), f=>f(1 DOWNTO 0), Cout=>xCout(0), BP=>xBP(0), BG=>xBG(0), SLout=>xSL(0), SRout=>SRout);

stage0b: alu2lca PORT MAP(Cin=>xxCout(0), SLin=>xSL(0), SRin=>xSR(1), sel=>sel, a=>a(3 DOWNTO 2),

b=>b(3 DOWNTO 2), f=>f(3 DOWNTO 2), Cout=>xCout(1), BP=>xBP(1), BG=>xBG(1), SLout=>xSL(1), SRout=>xSR(0));

stage0c: alu2lca PORT MAP(Cin=>xxxCout(2), SLin=>xSL(1), SRin=>xSR(2), sel=>sel, a=>a(5 DOWNTO 4),

b=>b(5 DOWNTO 4), f=>f(5 DOWNTO 4), Cout=>xCout(0), BP=>xBP(2), BG=>xBG(2), SLout=>xSL(2), SRout=>xSR(1));

stage0d: alu2lca PORT MAP(Cin=>xxCout(1), SLin=>xSL(2), SRin=>SRin, sel=>sel, a=>a(7 DOWNTO 6),

b=>b(7 DOWNTO 6), f=>f(7 DOWNTO 6), Cout=>xCout(1), BP=>xBP(3), BG=>xBG(3), SLout=>SLout, SRout=>xSR(2));

stage1a: lca2gen PORT MAP (c0=>Cin, p0=>xBP(0), p1=>xBP(1), g0=>xBG(0), g1=>xBG(1), c1=>xxCout(0), BP=>xxBP(0), BG=>xxBG(0));

stage1b: lca2gen PORT MAP (c0=>xxxCout(2), p0=>xBP(2), p1=>xBP(3), g0=>xBG(2), g1=>xBG(3),

c1=>xxCout(1), BP=>xxBP(1), BG=>xxBG(1));

stage2: lca2gen PORT MAP (c0=>Cin, p0=>xxBP(0), p1=>xxBP(1), g0=>xxBG(0), g1=>xxBG(1),

c1=>xxxCout(2), c2=>Cout, BP=>BP, BG=>BG);

END alu;

Block Diagram

Diagram A

Functional Simulations

Select = ‘000’ Zero FunctionFigure 3a

Select = ‘100’ Shift Left Logical FunctionFigure 3b

Select = ‘101’ Shift Right Logical FunctionFigure 3c

Select = ‘111’ Add w/ Carry FunctionFigure 3d

Select = ‘111” Subtract FunctionFigure 3e

DiscussionThis part of the pre-lab concentrated on putting the components

already completed together and creating an 8-bit LCA ALU. As seen in Diagram A, 4 2-bit ALU’s were connected together and to a pair of LCA generators to create a new, larger ALU. Figure 3a shows the zero function, Figure 3b shows the SLL Function, Figure 3c shows the SRL function. Figure 3d shows the adder portion of the ALU which uses the carry-in to help with arithmetic. Figure 3e Shows the subtract function. This function is identical to the adder function accept the second number is inverted (1’s complement) and the carry must manually be activated (2’s complement). A-B is the same as A + -B. The carry-in was kept manual in order to simplify the circuit and increase performance.

Section 4Use the Quartus II graphical editor to create a .bdf file that integrates the 8-bit ALU with two 7-segment LED display decoders that you used in Lab 2.

Block Diagram

Diagram B

Timing Simulation

Figure 4aDiscussion

This part of the pre-lab was the culmination of the earlier parts. As seen in Diagram B, the ALU created in Section 3 was connected to a 7-segment display, in order to display the result of the given operation on the BTU-Board in lab. The gate delays can be seen in Figure 4a depending on which operation is performed. This has to do with the complexity of certain parts of the ALU’s and the LCA generators during certain operations.

In-LabThe lab itself consisted of testing out the finalized ALU, which

went smoothly, and then to design a 16-bit ALU and then simulate it. The 16-bit ALU consisted of combining two 8-bit ALU’s can connecting the Cin to the Cout and then the SRin and SLin to the SRout and SLout, respectively. Also, the LCA generators need to be connected, the 2nd

and 3rd one to be precise. Both LED displays were used to output the result.

Summary & ConclusionsThis lab was very similar to the adder construction done in a

previous lab, but instead of combining adders to LCA generators, ALU’s are connected. The LCA generators again help to increase performance during the add/subtract operations compared to RC adders.

The execution of the lab was pretty straight forward. The only problem encountered was with the malfunctioning dip-switched the right-most switch on both banks is not operable. The problem is that the shift right out cannot be tested for since the right-most switch will not change. In the scope of things, however, it is a very minor problem.

Lab4 Report Eel4712

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