CENG450 Project 16-bit MIPS Processor

Format AIbrahim Hazmi - 2017

2 Simple CPU

Outline

3 CPU with Control Unit

5 Control Unit approaches

4 CPU, Control Unit & Memory

1 Register File & ALU

Register File & ALU8 16-bit registers: r0, r1, r2, r3, r4, r5, r6, r7

Read operation: the register file gets rd_index1 and rd_index2 to deliver the corresponding rd_data1 and rd_data2.

Write operation: the register file writes the value on wr_data to the register determined by wr_index, when wr_en is one.

alu_mode ALU operation0 Nop1 Add2 SUB - Subtract3 MUL- Multiply4 NAND5 SHL - Shift Left Logical6 SHR - Shift Right Logical7 TEST

Register File

ALU

Some notes about ALU➡ ALU components can be built behaviourally or

structurally. ➡ Signed data type is recommended for (+/-/*)

operations, using “ieee.std_logic_arith.all”. ➡ Multiplication (*) results in 32-bit output. The

decision on the higher 16-bit should be made. ➡ SHL & SHR can be performed using Barrel

Shifter or by a simple LOOP of a single shift, e.g, for i in 1 to 16 loop if i <=conv_integer(in2) then temp := temp(6 downto 0) & ‘0'; end if; end loop;

➡ TEST is the only instruction that generates Flags

More notes about ALU

➡ If you decide to ignore the higher 16-bit of the output in Multiplication (*), It it recommended that you make your multiplier 8-bit internally: result <= std_logic_vector(unsigned(in1(7 downto 0)) * unsigned(in2(7 downto 0)));

➡ Otherwise, you need to have another output port in order to accommodate the higher and lower 16-bit result2: out std_logic_vector(15 downto 0); : : signal r32: std_logic_vector(31 downto 0); : : r32<= std_logic_vector(unsigned(in1) * unsigned(in2)); result <= r32(15 downto 0); result2<= r32(31 downto 16);

Simple CPU

Simple CPU➡ CPU entity here has 8-inputs and 3-outputs Ports. ➡ RF & ALU are defined as components, and

rd_data1/rd_data2 as signals, in the CPU body. ➡ Wr_data is required to feed the targeted Registers

with external data before reading from them. ➡ RF & ALU have the same clk & rst signals ➡ Testbench input samples should fall into 4 parts:

➡ Registers filling via (wr_data) ➡ Registers reading ➡ ALU operation select via (alu_mode) ➡ Register write back (result to wr_data of RF)

CPU with Control Unit

➡ Control Unit (CU) contains the control word that can be divided into two parts: ➡ RF / ALU control signals, e.g., rd_indexX,

wr_index, and alu_mode, which are within IR. ➡ Select & Enable signals, e.g., wr_en, which

are generated in CU at specific time sequence ➡ In this section, (CU) should have about 4 stages,

to accommodate the same cases in the testbench:

CPU with Control Unit

CPU with Control Unit

CPU, Control Unit & Memory

➡ Control Unit (CU) here has more stages to allow for ROM access and PC Fetch:

➡ CU should match the basic Instruction Cycle as:

CPU, Control Unit & Memory

Another presentation of OUT port

➡ With another presentation of OUT port, CU be presented as:

CPU, Control Unit & Memory

The Essential need for a control unit

➡ Control Unit (CU) is an essential component of the microprocessor since it acts like the heart, pumping the control pulses to make the data-path alive

➡ RF / ALU control signals can be wired directly from IR to the data-path (RF / ALU select control.

➡ But Select & Enable signals need to be generated in CU with a sequencer to control their timing.

➡ So, (CU) must be present in the design, either as an FSM, or a Microcoded Controller.

Implemented through use of sequential logic units as a finite state machine (FSM)

Organized as a sequence of micro-instructions with a control memory.

Control Unit (CU) approachesHardwired CU (FSM) Microprogrammed CU

library IEEE;use IEEE.STD_LOGIC_1164.ALL; --Sequence detector for detecting the sequence "1011".entity seq_det isport(   clk   : in std_logic;      --clock signal        reset : in std_logic;      --reset signal        S_in  : in std_logic;      --serial bit Input sequence            S_out : out std_logic);    -- Output         end seq_det;architecture Behavioral of seq_det is --Defines the type for states in the state machinetype state_type is (S0,S1,S2,S3,S4); signal Current_State, Next_State : state_type; begin process(clk) -- Synchronous Processbegin    if( reset = '1' ) then           --Synchronous Reset        Current_State <= 'S0';     elsif (clk'event and clk = '1') then   --Rising edge of Clock        Current_State <= Next_State    end if;end process;

            when S1 =>                S_out <= '1';                   if ( S_in = '0' ) then                    Next_State <= S3;                else                        Next_State <= S2;                end if;             when S2 =>                S_out <= '0';                   if ( S_in = '0' ) then                    Next_State <= S0;                else                        Next_State <= S3;                end if;             when S3 =>                S_out <= '1';                   if (S_in = '0' ) then                    Next_State <= S2;                else                        Next_State <= S4;                end if;             when S4 =>                S_out <= '1';                   if ( S_in = '0' ) then                    Next_State <= S2;                else                        Next_State <= S1;                end if;             when others =>                NULL;        end case;    end if;end process; 

Process(Current_State, S_in) -- Combinational Process    begin        case Current_State is             when S0 =>                                      S_out <= '0';                if ( s_in = '0' ) then                    Next_State <= S0;                else                        Next_State <= S1;                end if;

FSM Example

library IEEE;use IEEE.STD_LOGIC_1164.ALL; entity Mult is port(CLK, St, K, M: in std_logic; Load, Sh, Ad, Done: out std_logic);end Mult;architecture SMbehave of Mult issignal State, Nextstate: integer range 0 to 3;begin process(St, K, M, State) begin Load <= '0'; Sh <= '0'; Ad <= '0'; Done <= ‘0';case State is when 0 => if St = '1' then Load <= '1'; Nextstate <= 1; else Nextstate <= 0; end if; when 1 => if M = '1' then Ad <= '1'; Nextstate <= 2; else Sh <= '1'; if K = '1' then Nextstate <= 3; else Nextstate <= 1; end if; end if;

when 2 => Sh <= '1'; if K = '1' then Nextstate <= 3; else Nextstate <= 1; end if; when 3 => Done <= '1'; Nextstate <= 0; end case; end process;process(CLK) begin if rising_edge(CLK) then State <= Nextstate; end if; end process;end SMbehave;

Another FSM Example

library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity mult4X4_micro is port(Clk, St: in std_logic; Mplier, Mcand: in std_logic_vector(3 downto 0); Product: out std_logic_vector(7 downto 0); Done: out std_logic);end mult4X4_micro;architecture microprogram of mult4X4_micro istype ROM is array(0 to 5) of std_logic_vector(11 downto 0);constant control_store: ROM := (X"010", X"D28", X"630", X"E44", X"952", X"C01");signal ACC: std_logic_vector(8 downto 0); alias M: std_logic is ACC(0);signal TMUX, Load, Ad, Sh, K: std_logic;signal counter: std_logic_vector(1 downto 0) := “00";signal uAR: std_logic_vector(2 downto 0) := "000";signal uIR: std_logic_vector(11 downto 0) := X”000”;alias TEST: std_logic_vector(1 downto 0) is uIR(11 downto 10);alias NSF: std_logic_vector(2 downto 0) is uIR(9 downto 7);alias NST: std_logic_vector(2 downto 0) is uIR(6 downto 4);begin Load <= uIR(3); Ad <= uIR(2); Sh <= uIR(1); Done <= uIR(0); Product <= ACC(7 downto 0); K <= '1' when counter = "11" else ‘0';with TEST select TMUX <= St when "00", M when "01", K when "10", '1' when others;

controller: process(Clk) begin if falling_edge(Clk) then uIR <=control_store(conv_integer(uAR)); end if; if rising_edge(Clk) then if TMUX = '0' then uAR <= NSF; else uAR <= NST; end if; if Sh = '1' then counter <= counter + 1; end if; end if; end process;datapath: process(Clk) begin if rising_edge(Clk) then if Load = '1' then ACC <= "00000" & Mplier; end if; if Ad = '1' then ACC(8 downto 4) <= ACC(8 downto 4) + Mcand; end if; if Sh = '1' then ACC <= '0' & ACC(8 downto 1); end if; end if; end process; end microprogram;

Microprogram Example

library IEEE;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity Parity_Gen is port(OT: in std_logic; X: in std_logic_vector(3 downto 0); Y: out std_logic_vector(4 downto 0));end Parity_Gen;architecture Table of Parity_Gen is type OutTable is array(0 to 15) of std_logic; signal ParityBit: std_logic; constant OT: OutTable := ('1','0','0','1','0','1','1','0', '0','1','1','0','1','0','0','1');begin ParityBit <= OT(conv_integer(X)); Y <= X & ParityBit;end Table;library IEEE;use ieee.std_logic_1164.all;entity MUX4to1 is port(I: in std_logic_vector(3 downto 0); S: in std_logic_vector(1 downto 0); F: out std_logic);end MUX4to1;architecture Dataflow of MUX4to1 isbegin with S select F <= I(0) when "00", I(1) when "01", I(2) when "10", I(3) when "11";end Dataflow;

Microprogram Example Continue

References

https://en.wikipedia.org/wiki/Control_unit

https://voer.edu.vn/file/7173

http://people.uncw.edu/tagliarinig/Courses/242/RegisterTransfer/BasicControlUnit.gif

http://www.slideshare.net/mekind/basic-computer-organization-and-design-30538899

http://www.vlsiencyclopedia.com/2011/12/finite-state-machine-coding-in-vhdl.html

http://faculty.weber.edu/snaik/ECE3610/09Lec9.pdf

ece.citadel.edu/hayne/elec418/418_05.ppt

Register File