LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory...

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LAB1 Summary Zhaofeng SJTU.SOME

Transcript of LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory...

Page 1: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

LAB1 Summary

Zhaofeng

SJTU.SOME

Page 2: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

Embedded Software Tools

CPU

Logic Design Tools

I/O

FPGA

Memory

Logic Design Tools

FPGA + Memory + IP +High Speed IO

(4K & Virtex)

Embedded Software Tools

CPU

Inte

grat

ion

of F

unct

ions

Inte

grat

ion

of F

unct

ions

TimeTime

Logic Design Tools

Embedded Software Tools

Logic + Memory + IP +

Processors + RocketIO

(Virtex-II Pro)

Programmable Systemsusher in a new era of system

design integration possibilities

Programmable Systemsusher in a new era of system

design integration possibilities

Integration in System Design

Page 3: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

PowerPC405 Core

Dedicated Hard IPFlexible Soft IP

RocketIO

PowerPC-based

Full system customization to meet

performance, functionality, and cost goals

DCR Bus

UART GPIOOn-Chip

PeripheralHi-Speed

PeripheralGB

E-Net

e.g.Memory

Controller

Arb

iter

On-Chip Peripheral Bus

OPB

Arb

iter

Processor Local Bus

Instruction Data

PLB

DSOCMBRAM

ISOCMBRAM

Off-ChipMemory

ZBT SRAMDDR SDRAM

SDRAM

BusBridge

IBM CoreConnect™on-chip bus standardPLB, OPB, and DCR

Page 4: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

MicroBlaze Processor-Based

Flexible Soft IPMicroBlaze32-Bit RISC Core

UART 10/100E-Net

Memory Controller

Off-ChipMemory

FLASH/SRAM

Fast Simplex Link

0,1….7

CustomFunctions

CustomFunctions

BRAM Local Memory

BusD-CacheBRAM

I-CacheBRAM

ConfigurableSizes

Arb

iter

Processor Local Bus

Instruction Data

PLBBus

Bridge

PowerPC405 Core

Dedicated Hard IP

Arb

iter

Processor Local Bus

Instruction Data

PLBBus

BridgeBus

Bridge

PowerPC405 Core

Dedicated Hard IP

PowerPC405 Core

Dedicated Hard IP

PowerPC405 Core

Dedicated Hard IPPossible inVirtex-II Pro

Hi-SpeedPeripheral

GB E-Net

e.g.Memory

Controller

Hi-SpeedPeripheralHi-Speed

PeripheralGB

E-NetGB

E-Net

e.g.Memory

Controller

e.g.Memory

Controller

Arb

iter OPB

On-Chip Peripheral Bus

CacheLink

SRAM

Page 5: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

Embedded Design in an FPGA

• Embedded design in an FPGA consists of the following:– FPGA hardware design– C drivers for hardware– Software design

• Software routines• Interrupt service routines (optional)• Real Time Operating System (RTOS) (optional)

Page 6: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

Embedded Development Kit

• What is Embedded Development Kit (EDK)?

– The Embedded Development Kit is the Xilinx software suite for designing complete embedded programmable systems

– The kit includes all the tools, documentation, and IP that you require for designing systems with embedded IBM PowerPC™ hard processor cores, and/or Xilinx MicroBlaze™ soft processor cores

– It enables the integration of both hardware and software components of an embedded system

Page 7: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

Embedded DevelopmentTool Flow Overview

Data2MEM

Download Combined Image to FPGA

Compiled ELF Compiled BIT

RTOS, Board Support Package

EmbeddedDevelopment Kit

Instantiate the ‘System Netlist’ and Implement

the FPGA

?

HDL Entry

Simulation/Synthesis

Implementation

Download BitstreamInto FPGA

Chipscope

Standard FPGAHW Development Flow

VHDL or Verilog

System NetlistInclude the BSPand Compile theSoftware Image

?

Code Entry

C/C++ Cross Compiler

Linker

Load SoftwareInto FLASH

Debugger

Standard EmbeddedSW Development Flow

C Code

Board SupportPackage

12 3 Compiled BITCompiled ELF

Page 8: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

Embedded System Tools• GNU software development tools

– C/C++ compiler for the MicroBlaze™ and PowerPC™ processors (gcc)

– Debugger for the MicroBlaze and PowerPC processors (gdb)

• Hardware and software development tools– Base System Builder Wizard– Hardware netlist generation tool: PlatGen– Software Library generation tool: LibGen– Simulation model generation tool: SimGen– Create/Import Peripherals Wizard– Xilinx Microprocessor Debug (XMD)– Hardware debugging using ChipScope™ Pro Analyzer cores– Eclipse IDE-based Software Development Kit (SDK)– Application code profiling tools– Virtual Platform generator: VPGen– Flash Writer utility

Page 9: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

Embedded System Tools

• Board Support Packages (BSPs)– Standalone BSP– Wind River VxWorks– MontaVista Linux– Xilinx MicroKernel (XMK)

• Xilinx Platform Studio– Xilinx Platform Studio (XPS) is a graphical Integrated D

esign Environment (IDE) that incorporates all the Embedded System Tools for seamless creation of hardware and software components and, optionally, a verification component

Page 10: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

Xilinx Platform Studio (XPS)See notes section for detailed explanation

Page 11: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

XPS Functions

XPS

HW/SWSimulation

HW/SWDebug

Hardware Design

SoftwareDesign

• Project management– MHS or MSS file– XMP file

• Software application management

• Platform management– Tool flow settings– Software platform settings– Tool invocation– Debug and simulation

Page 12: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

Lab1 ESD on FPGA

• Lab1.1 Simple Hardware Design

• Lab1.2 Adding IP to a Hardware Design

• Lab1.3 Adding Custom IP

• Lab1.4 Writing Basic Software Applications

• Lab1.5 Advanced Software Writing

• Lab1.6 Cross Debugging

Page 13: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

Create Embedded System using BSB

PPC

PLBBus

PLB2OPB

PLB BRAM Cntlr

OPBBus

PLB BRAM

PLB BRAM Cntlr PLB BRAM

INTC

GPIO

Timer

UART

MY IP LEDs

ICON

IBA

GPIO Push Buttons

DIP Switches

Verify HW Operation with generated Test Application

Page 14: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

Add GPIO Cores

PPC

PLBBus

PLB2OPB

PLB BRAM Cntlr

OPBBus

PLB BRAM

PLB BRAM Cntlr PLB BRAM

INTC

GPIO

Timer

UART

MY IP LEDs

ICON

IBA

GPIO Push Buttons

DIP Switches

Add SW code to read state of DIP switches and Push Buttons and display on hyperterm

Page 15: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

Summary

• BSB can be used to create a simple processor system targeting a specific hardware board– Generates an MHS text file that describes the embedded system h

ardware– Generates a Test Application to test memory and peripherals

• Platform generator converts the MHS to a system netlist• The ISE tools generate a bitstream from the system netlist• The bitstream was initialized with the software test applicat

ion in EDK• The bitstream was downloaded to the XUP board• Output was displayed on hyperterminal

Page 16: LAB1 Summary Zhaofeng SJTU.SOME. Embedded Software Tools CPU Logic Design Tools I/O FPGA Memory Logic Design Tools FPGA + Memory + IP + High Speed IO.

两点说明• 外部管脚与 UCF

• 系统工作示意图


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