Lab1 Document

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ECE745:ASICVerification

LabAssignment#1

QuestaSystemVerilogTutorial


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PART1:GettingStartedwiththeEnvironment

LabIntroduction

Inthislaboratoryexercise,youaregoingtocompletetheQuestatutorialatNCSUandgetyourselfacquaintedwithsomeofthefundamentalcomponents(interface,program body and top-level integration) of a testbench. You will also learn torecognizeafewbasicdata-typesandtheirusageinatestbenchenvironment.Thebasicideaistoa)GetthefeelforatypicaltestbenchusingSystemVerilogandb)togetcomfortablewiththeQuestaverificationenvironmentc)TogetacquaintedwiththeDUTthatwillbeusedinalltheLaboratoryexerciseshenceforth.

ToolIntroduction

QuestaSimis part of theQuestaAdvancedFunctionalVerificationPlatformandisthe latest tool inMentor Graphics tool suite for Functional Verification. The toolprovidessimulationsupportforlateststandardsofSystemC,SystemVerilog,Verilog2001standardandVHDL.ThistoolisanadvancementoverModelsiminitssupportfor advanced Verification features like coverage databases, coverage drivenverification, working with assertions, SystemVerilog constrained-randomfunctionality.

Step1:EstablishingtheDesignEnvironmentforcompilation

Onetimesetupforagivendirectoryusedforsimulation:

Eachtimeyoucreateadirectoryforsimulationsyouwouldhavetodothefollowing

prompt%> add questasim63 OR prompt%> add modelsim

Copythemodelsim.inifilethatcomeswiththistutorialintothedirectory.ThisfilesetsupthenecessarydefaultsfortheQuestatool.

Create the library into which all the design units will be compiled. Do this byperforming

prompt%> vlib mti_lib

(Note that the name mti_lib corresponds to the variable work within themodelsim.inifileandisthelibrarytowhichallthesourcecodewouldbecompiledtocreateadesignsingleentity).Notethatinsomecases,ifthecompilationseemstocrashforareasonyouthinkisincorrect,itwouldbeadvisabletodeletethemti_libdirectory(Use:\rmrfmti_libORvdelall)andre-createitasshownabove.


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Setupforsimulationswithinadirectoryforagivensession:

Weassumethepreviousstephasalreadybeenfollowed.Letusassumeadirectoryhasbeensetupupcorrectlyandyoucomeintothisdirectoryforafuturesimulation.Youwouldstillneed torun the following commands each timeyou startaset ofsimulationsforagivendesignwithinadirectory.

setpathstotheModelsimtool:

prompt%> add questasim63 OR prompt%> add modelsim

setenvironmentvariableMODELSIMtomodelsim.ini

prompt%> setenv MODELSIM modelsim.ini

Atthispoint,allthepathsettingsaregoodtogofortheexecutablesassociatedwithQuesta.ItisassumedherethatuserisawareoftherequirementsforremoteaccessfromaWindowsplatform.Ifnot,theinformationcanbeobtainedfromtheremoteaccesspage.

CompilationandSimulation

TheQuestatoolenablescompilationofmultipledesign/verification/modelingunits(eachofwhichmightbeinadifferentlanguage)intoacommonlibrary(calledtheworkinglibrary)andacommondesignrepresentation.Thisenableseachindividualunit of the entire simulation to be compiled independently and incremental

compilationtobeperformed.Atthispointitmustbestatedthatthecompilationofthesourcecodecaneitherbedonewithinthesimulationenvironment(GUI)oronthe command prompt. The simulation though MUST be performed within thesimulation environment. In the interest of simplicity,weshallbeperforming thecompilationofthesourcecodeonthecommandpromptoftheUNIX/Linuxterminalandprovidingabasicunderstandingofthetoolcapabilities.

Alltheworkshouldbedonewithinthesamefoldersay/Simulation/


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Tobeginthecompilationandsimulationprocess,pleasedownloadthefollowingintoadirectoryofyourchoice(/Simulation/)

TheProtectedandunprotectedVerilogRTLfortheDesignUnderTest(DUT):

Basic_ALU.vpTheSystemVerilog(SV)TestbenchforthisRTL:

Basic_ALU.tb.sv Basic_ALU.if.sv Basic_ALU.test_top.sv

ThiscorrespondstoaverybasicALUblocktointroduceyoutothetools.

TheSystemVerilog(SV)TestbenchforthisRTL:

Basic_ALU.if.svthecreationanduseaninterfacetotheDUTwithaclockingblockandamodport.

Basic_ALU.tb.svthecreationofaprogramwhichprovidesconstrained

stimulustotheDUT.ThiscodehasbeenwrittentoprovidetheuseraverybasicintroductiontoatypicalprogramstructurewithtasksandpassingofsignalsintotheDUT.

Basic_ALU.test_top.svthecreationofatoplevelintegrationoftheDUT,theinterfaceandtheprogramforsendingstimulustothedesign.

ForthistutorialthetestbenchisonlygoingtobeusedforthecreationofconstrainedstimulusandforsendingthesestimuliintotheDUT.

Atthispointwecaneitherdostep3intheGUIenvironmentoratthecommandprompt.Weshallcontinuewiththecommandprompt.

Thenextstepsneedtobeperformedeachtimeacodechangeisperformed

andthechangesneedtobereflectedinthesimulations.

Step1:Compilationofsourcecode

CompiletheVerilogRTLModel:AgoodfeatureisthatVerilog(protectedanunprotected)sourcefilescanbecompiledoutoforder.Thus,webeginbycompilingtheprotectedverilogfilesbydoing:

prompt%> vlog *.vp


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Whichresultsinthemessage:

QuestaSim vlog 6.3c Compiler 2007.09 Sep 11 2007

-- Compiling module Basic_ALU

Top level modules:

Basic_ALU

WhichimpliesthatthehighlevelmoduleinthehierarchythatwasdiscoveredisBasic_ALU.

CompiletheSystemVerilogTestbench:TheSVcodesharesthesameabilitytobecompiledinanyorder.Thisholdsaslongastheincludesfromonefiledonotbeatonthoseinanotherfile.Itisalwayssuggestedtofollowanorderedcompilation.Thus,

SystemVerilogcompilationcanbedonebyrunningthecommands

prompt%> vlog -sv -mfcu Basic_ALU.if.sv Basic_ALU.tb.sv Basic_ALU.test_top.sv

Asuccessfulcompilationofthesystemverilogfilesshouldspitoutthefollowingmessage:

QuestaSim vlog 6.3c Compiler 2007.09 Sep 11 2007-- Compiling interface Basic_ALU_interface-- Compiling program Basic_ALU_test-- Compiling module Basic_ALU_test_top

Top level modules:

Basic_ALU_test_top

ThemostimportantthingtonoteinthisexampleisthatthetopmostdesignunitisBasic_ALU_test_top which has an instance of the "testbench Basic_ALU_test"connectedtotheDUT"Top"throughtheinterface"ALU_Interface".

Step2:Simulationofdesign

Wecannowsimulatethedesignunit(testbench+DUT)byinvokingthesimulator(vsim)withthetopleveldesignunit(Basic_ALU_test_top).

% vsim -novopt Basic_ALU_test_top

ThisleadstotheinvocationofthesimulationGUIwiththreewindows:Workspace,Objectsandtranscript.Tobeginwith,notethatthepromptisof theformVSIM#>,where#correspondstothenumberofcommandsissuedinthesimulationmode.Also, at this point the Workspace window would have tabs corresponding thesimulation hierarchy (sim), the source files (Files) and the analysis tool for theregister arrays in the system if any (Memories). The objects window containsvariables, wires, regs, variables etc their values and their characteristics. Anexampleofthewindowatthispointisshownbelow:


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Inthefigurebelow,thehierarchycorrespondingtotheDUThasbeenexpandedanditscontentspopulatetheobjectswindowbyvirtueofclickingonthenameDUTontheworkspacewindow.


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Atthispointweneedtohaveameansofviewingthevaluesthatareofinteresttous.Toaddthesignalsofinteresttothewaveformviewer,wewouldneedtoselectthesefromtheObjectswindow->rightclick->addtowave->selectsignals.Thiscanalsobedoneforagiveninstance in theWorkspacewindowbut thismightneedto an

excessivenumberofvalueswhichmightbeoverkill.AnexamplesetofsignalsintheObjectwindowhavebeenhighlightedandsenttothethewaveformwindowbelow:


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The execution ofthe above leadstothe appearance ofthewaveformwindow.Tobegin with, this window could be a part of (docked with) the GUI but can beseparated(undocked)fromtheGUIframebyhittingthebutton.Thiscreatesanewwindowwith the signalsandvariablesofchoice populating the frameto the left.Thereisgoingtobeaneedtoadjusttheframestomakethethenamesandsignalvaluesappearinamannerfavorabletoyou.Weleaveituptoyoutoplayaround

with the waveform window. If the design is not too big, then you can run thecommandbelowtologallsignalsatalllevelsofhierarchy.Ifthecommandbelowwas not executed prior to a simulation run, only those signals specified in thewaveform window wouldbe logged and hence any new signal of interestwouldrequirerestartingofthesimulation:

VSIM#> log -r /*

Torunthesimulationweneedtorunthecommand(fora200nsadvancementofsimulationtimeORafullrun)

VSIM#> run 200ns (or any other time that you would like) OR VSIM#>

run -all (for a full run of the simulation)

Itmustbenotedthatthetestbenchmusthavetheabilitytofinish(using$finish,exit)atsomepointduringthesimulationtodoa"run-all".Else,thesimulationwouldruniterateforever.

Onissuingtheabovecommand,thecontentsofthewaveformwindowcouldbezoomedin.Tozoomusethestandardzoombuttons(maginifyingglass).Auseful


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shortcutistousehit"f"tozoomfull(the200nsthatthesimulationhasbeenrun).Thewaveformwindowthatyouseeshouldmirrorwhatyouseebelowforthecasewherewehaveaddclock,reset,enable,aluin1,aluin2,aluoperation,aluopselect,etc.fromtheobjectwindowtothewaveform.Thefigurealsoshowsyouoneotherusefulfeaturewhereyoucanchangetheradixofthenumericalrepresentationto

onethatyouarecomfortablewith.

Toendasimulationrun

VSIM#> exit

Also,ifchangesweremadetothecodewhiletheGUIwasup,youcanrecompile(ontheUNIXcommandpromptifyousowish)andthenre-startthesimulationbyrunning(assumingwewanttorecompileALLthefiles).

VSIM#> vlog *.sv -sv -mfcuVSIM#> vlog *.vpVSIM#> vlog *.vVSIM#> restart -f

Wecouldhaverecompiledjustthefilesthatweremodified.


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Lab1Questions:

1. Whatdoesrepeat(5) @(ALU_Interface.cb) do?

2. Describethefunctionalityandthetimingcharacteristicsoftheresettask

3. Therearemultipletasksdefinedinthetestbenchprovided.Basedontheconceptsconveyed in Lecture 1, please state the layers (in a layered testbench) that

the tasks would belong to.

4. What lines would you modify to make the testbench run 10 times?

5. What set of inputs would you send in (relevant input signals only need to be stated)

for the following to be executed:a. Addthenumbers32and67.

b. Subtract579from4967.

c. PerformaNOToperationonthebinaryequivalentof876

d. ANDtogether579and982

e. ORtogether579and982


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f. XORtogether579and982

6. SendineachoftheinputsfromthepreviousquestionintotheDUTbymodifyingthetestbenchprogram.Also,determinewhethertheoutputsare

alongexpectedlines.Ifnot,statetheerrors.

7. Observetheoperationoftheclock,resetandenablesignals.Determineiftheyareoperatingalongexpectedlinesandifnotstatetheerrors.

8. LocateandDocumentanybugsfoundinthespacebelow.Beasspecificaspossible.Youmayneedtorunstimuliotherthantheonesyougenerated

above.


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Lab1SubmissionRequirements:

ThegeneratedinputsandresultingoutputsareshownintheQuestaSimlogfrom$displaystatementswithinthetestbench.

Makesurethattheseresultsaredisplayedfromeachofyourinputsbyrunningyourprogramjustasstatedinthetutorial.Thesamefilenames(Basic_ALU.tb.sv,Basic_ALU.test_top.sv, Basic_ALU.if.sv)needtobeused.

Followthefollowingstepsforsubmissions(Solaris/Linuxonlyplease)!mkdirLab1 (createsthedirectoryLab1)!copyalltheSystemVerilogfilesintotheLab1directory!AnsweralltheabovequestionsinafilecalledLab1.doc andcopythisintothe

Lab1directory!Zipthefileusingthecommand>zip Lab1.zip Lab1/* !Submitthezipusingthesubmitutilityonthecoursewebpage.

Lab1 Document

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