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EE471 Lab 1 Autumn 2010

MIPS 32 by 32 Register File

Due by 5:00, 30/9/10

Introduction:

For this lab you are to onstrut a 32 by 32 re!ister "ile usin! #erilo!$ %he

re!ister "ile is intro&ue& in ha'ter 4 o" the lass te(t1$ )ithin the 32 by 32

re!ister "ile is an array o" 32 &i""erent 32bit re!isters$ %hese re!isters must beonstrute& "rom D flip-flops *'ositi#e e&!e+tri!!ere&$ -ote that "or .

re!ister ero is har&ire& to alays out'ut the #alue ero, re!ar&less o" hat may

or may not be ritten to it$ %he "i!ure belo shos a blo &ia!ram o" a re!ister"ile *this is a mo&i"ie& re'ro&ution o" "i!ure 4$7 on 'a!e 310 o" the te(tboo$

ea& e!ister 1 an& ea& e!ister 2 selet the re!isters hose #alues are out'ut

on the ea& Data 1 bus an& ea& Data 2 bus res'eti#ely$ %he )rite e!isterin'ut bus &esi!nates the re!ister into hih the in"ormation on the )rite Data bus

is to be ritten hen the e!)rite ontrol si!nal is hi!h$

Implementation:

A sim'le im'lementation o" the 32 by 32 . re!ister "ile an be ma&e usin!e!isters om'ose& o" D "li'+"lo's, a 5:32 enable& &eo&er, an& to lar!e 32(32

to 32 multi'le(ors$ %his is shon in the "olloin! blo &ia!ram *note that the

lo is omitte& "or larity$

16om'uter 8r!aniation an& Desi!n by atterson an& ennessy

a!e 1

5

5

5

3 2

3 2

3 2

R e a d

R e g i s t e r 1R e a d

R e g i s t e r 2

W r i t e

R e g i s t e r

W r i t e

D a t a

R e a dD a t a 1

R e a d

D a t a 2

R e g W r i t e

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EE471 Lab 1 Autumn 2010

Eah re!ister is sim'ly an array o" 32 D "li'+"lo's, the blo re'resentation o"hih is as "ollos$

a!e 2

0

R e g i s t e r 1

Multiplexor

3 2

R e g i s t e r 2 3 2

R e g i s t e r 3 1 3 2

3 2

Multiplexor

3 2

3 2

3 2

3 2

Decoder 3 2

3 2

3 2

5

5

R e a d

D a t a 2

R e a d

D a t a 1

R e a d R e g i s t e r 1

R e a d R e g i s t e r 2

W r i t e D a t a

5

R e g W r i t e

W r i t e R e g i s t e r

R e g i s t e r R e g i s t e r 3 2 3 2D a t a I n D a t a O u t

W r i t e E n a b l e

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EE471 Lab 1 Autumn 2010

)here the D in'ut o" eah D "li'+"lo' orres'on&s to a sin!le bit in the 32 bit &ata

in'ut bus an& the ; out'ut o" eah D "li'+"lo' orres'on&s to the a''ro'riate bitin the 32 bit &ata out'ut bus$ %he enable o" e#ery D "li'+"lo' is onnete& to the

same rite enable in'ut si!nal$ %his element ill also reei#e a lo in'ut,

hih synhronies the re!isters$ -ote that the lo an& the rite enable arese'arate si!nals$ %he lo is a 'ure, 'erio&i si!nal ith no !lithes or other

eir& beha#iors$ %he rite enable may ha#e !lithes an& haar&s, an& thus must

be mo&erate& by the lo < mae sure that ran&om transitions o" the riteenable, as lon! as they are not simultaneous ith the ati#atin! lo e&!e

*'ositi#e e&!e, &o not ause the re!ister to s'uriously !rab a ne #alue$

%he &eo&er selets hih re!ister reei#es the e!)rite ontrol si!nal as itsenable in'ut$ )hen a re!ister is not selete& its enable in'ut shoul& be "alse$

Also note that the least si!ni"iant out'ut line o" the &eo&er is "loatin! in the

blo &ia!ram "or the re!ister "ile$ %his is beause the ero re!ister is har&ire&

to ero so it &oes not nee& rite enable in'ut$ n "at, instea& o" usin! a re!ister,you an =ust har&+o&e the in'uts to the out'ut mu(es "or re!ister ero to all

eroes$

%he most &i""iult 'art o" this lab is onstrutin! the lar!e 32(32 to 32

multi'le(ors$ 8ne ay to &o this is to "irst onstrut a 32 to 1 multi'le(or an& use32 o" these 32 to 1 multi'le(ors to onstrut the lar!er 32(32 to 32 mu($

WR!I!": 8n this lab there is an easy ay *throu!h hierarhy an& a har& ay

to &o thin!s$ " you "in& yoursel" ritin! a L8% o" lines that are all i&ential,e(e't ith some bus in&e(es han!e&, you are &oin! it the AD ay < rea& the

setion in the tutorial on hierary>

#ab Re$uirements %applies to all labs&

1$ ?se the "ile 6re!stim$# as your testbenh$ @ou shoul& alter the testin! as neessary

to mae sure your unit ors$ %he %As ill ha#e their on testbenh "or use &urin!the &emos, so you must mae sure your re!ister "ile taes the same in'uts out'uts,

in the same or&er, as is 'resente& in the 'ro#i&e& testbenh$

2$ All lo!i must be !ate le#el, strutural$ %hat is, built "rom e('liit A-D, 8, -A-D,

-8, B8, -CE%E, et$ !ates$ -o assi!n statements *e(e't an assi!n to set aire to a onstant #alue or onnet ires to!ether, AE statements, et$

3$ All !ates must ha#e at most 4 in'uts$ @ou an ha#e 'roe&ures ith more in'uts *an&

an buil& lar!er !ates u' this ay, but the basi !ates you ill buil& your iruit outo" annot ha#e more than 4 in'uts$

4$ All !ates ha#e a &elay o" 50's$ roessor 'er"ormane ont be a !ra&in! riteria "or

the lass *unless you &o really ri&iulous thin!s, but you nee& &elay to sho hothin!s beha#e$

5$ @ou may onstrut a DFF beha#iorally "or use elsehere:module D_FF (q, d, clk); output q; input d, clk;

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EE471 Lab 1 Autumn 2010

reg q; // Indicate that q is stateholding

always @(posedge clk) // old !alue e"cept at edge q # d;endmodule

?se this struture to buil& u' all the other statehol&in! elements an& re!isters in your'ro=et$

$ )hen e !et to labs 3 an& 4, you an &o the ontrol lo!i beha#iorally, or as &ata"lo*assi!n statements$ %he &ata'ath annot be beha#ioral at all, e(e't "or the DFF, but

the ontrol an be built any ay you hoose$

'urn In:

For this lab you ill &emo the "untionality o" your re!ister "ile to the %As, an&

must also turn in, &urin! lass, the "olloin!:

1$ A 'rintout o" your o&e2$ Full hemati at the !ate le#el$ t ill liely be multi+le#el *i$e$ bo(es

on an u''er le#el ha#e a loer+le#el sheet ith the &etails$ ine this

&ia!ram ill rea''ear in all subseuent labs, 'hotoo'y it or &o iteletronially$

GG DE.8-%A%8- )% %E %As AE E;?ED, )E%E

@8? LAH )8I 8 -8% GG

" you &o not &emo your assi!nment, you automatially !et a 0$ .issin! your

&emo slot ithout 'rior a''ro#al ill im'ose a late 'enalty on the entire lab$

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