Lab Record Format
Transcript of Lab Record Format
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Experiment No:1
Date: 16– 09 – 2011
ADDERS
AIM
Design and implement a)Half adder
b)Full adder
c)Ripple carry adder using Verilog code.
SOFTWARES USED
1. ModelSim (X 111 !."d)
#. Xilin$ (%.1i)
&. 'erilog
. *t+,ae
CIRCUIT DIAGRAM
a)Half adder
b)Full adder
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
c)Ripple carry adder
TRUTH TABLE
a)Half adder
b)Full adder
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
4include 6H-.6
module 7a8tb/
reg ab/
,ire scout/
integer i/
H- H(scoutab)/
initial
begin
9dumpfile (67adump.cd6)/
9dumpars (#7a8tb.H)/
end
initial
begin
:ab;#<b""/
for(i1/i=/ii>1)
?1" :ab;i/
end
initial
?1"" 9finis7/
endmodule
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
!ii) Full Adder
De"i#$ M%dule
module F-(scoutabcin)/
input abcin/
output reg scout/
al,ays 0(abcin)
:couts;a>b>cin/
ndmodule
Te"& Be$c'
4timescale 1ns51ps
4include 6F-.6
module fa8tb/
reg abcin/
,ire scout/
integer i/
F- F(scoutabcin)/
initial
begin
9dumpfile (6fadump.cd6)/
9dumpars (#fa8tb.F)/
end
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
initial
begin
:abcin;&<b"""/
for(i1/i=@/ii>1)
?1" :abcin;i/
nd
initial
?1"" 9finis7/
ndmodule
!iii) ( Bi& Ripple Carry Adder
De"i#$ M%dule
module rca(scoutabcin)/
input A&B"Cab/
input cin/
output reg A&B"Cs/
output reg cout/
al,ays0(abcin)
begin
:couts;a>b>cin/
end
endmodule
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Te"& Be$c'
4timescale 1ns51ps
4include 6rca.6
module rca8tb/
reg A"B&Cab/
reg cin/
,ire A"B&Cs/
,ire cout/
rca r(scoutabcin)/
initial
begin
9dumpfile (6rcadump.cd6)/
9dumpars (#rca8tb.r)/
end
initial
begin
a<b""1"/
b<b"1""/
cin1<b1/
?#" a<b""11/
b<b""1"/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
cin1<b"/
?#" a<b"11"/
b<b"1""/
cin1<b"/
end
initial
?1"" 9finis7/
endmodule
OBSERATIO*
!i)Half Adder
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
!ii) Full Adder
!iii)( Bi& Ripple Carry Adder
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
RESULT
- Half -dder Full -dder and it Ripple Earry -dder 7as been Designed and'mplemented and ,aeforms 7ae been obtained.
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Experiment No: 2
Date: 14 – 09 – 2011
D FLIFLO
AIM
Design and implement D flipflop using Verilog code.
SOFTWARES USED
+, ModelSim (Versions)
-, Xilin$ (Versions)
., 'erilog
(, *t+,ae
CIRCUIT DIAGRAM
TRUTH TABLE
ROGRAM
De"i#$ /%dule
module dff1("1dcl+reset)/
input dcl+reset/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
output reg "1/
al,ays 0(posedge cl+)
begin
if (reset1<b")
begin
"d/
1(G")/
end
else
begin
"1<b"/
11<b"/
end
end
endmodule
Te"& be$c'
4timescale 1ns51ps
4include 6dff.6
module dfftb1/
reg d8t/
reg cl+8t/
reg reset8t/
,ire "8t18t/
integer i/
dff1 d1("8t18td8tcl+8treset8t)/
initial
begin
9dumpfile(6dffdump.cd6)/
9dumpars(#dfftb1.d1)/
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end
initial
begin
reset8t1<b"/
cl+8t1<b1/
d8t1<b1/
?#" d8t1<b"/
?#" d8t1<b1/
end
al,ays
begin
? cl+8t=Gcl+8t/
end
initial
?1"" 9finis7/
endmodule
OBSERATIO*
RESULT
D flipflop 7as been designed and implemented and ,aeforms 7as been obtained.
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Experiment No: 3
Date: 14 – 09 – 2011
01 FLIFLO
AIM
Design and implement IJ flipflop using Verilog code.
SOFTWARES USED
1. ModelSim (X 111 !."d)
#. Xilin$ (%.1i)
&. 'erilog
. *t+,ae
CIRCUIT DIAGRAM
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
TRUTH TABLE
ROGRAM
De"i#$ /%dule
module K+ff1("1K+cl+reset)/
input K+cl+reset/
output reg "/
output reg 1/
al,ays 0(negedge cl+)
begin
if (reset1<b")
begin
case(:K+;)
#<b""B""/
#<b"1B"1<b"/
#<b1"B"1<b1/
defaultB"(G")/
endcase
1G"/
end
else
begin
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
"1<b"/
11<b"/
end
end
endmodule
Te"& be$c'
44timescale 1ns51ps
4include 6dff.6
module dfftb1/
reg d8t/
reg cl+8t/reg reset8t/
,ire "8t18t/
integer i/
dff1 d1("8t18td8tcl+8treset8t)/
initial
begin
9dumpfile(6dffdump.cd6)/
9dumpars(#dfftb1.d1)/
end
initial
begin
reset8t1<b"/
cl+8t1<b1/
d8t1<b1/
?#" d8t1<b"/
?#" d8t1<b1/
end
al,ays
begin
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
? cl+8t=Gcl+8t/
end
initial
?1"" 9finis7/
ndmodule
OBSERATIO*
RESULT
IJ flipflop 7as been designed and implemented and ,aeforms 7as been obtained.
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Experiment NoB
Date: 14– 09 – 2011
(2+ MULTILE3ER A*D +2( DEMULTILE3ER
AIM
Design and implement L1 multiple$er and 1L demultiple$er using Verilog code.
SOFTWARES USED
1. ModelSim (X 111 !."d)
#. Xilin$ (%.1i)
&. 'erilog
. *t+,ae
CIRCUIT DIAGRA&M
a)(2+ /ul&iple4er
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
TRUTH TABLE
b)+2( de/ul&iple4er
CIRCUIT DIAGRAM
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
TRUTH TABLE
ROGRAM
a)/ul&iple4er
De"i#$ /%dule
module mu$(dso)/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
input A&B"Cd/
input A1B"Cs/
output reg o/
al,ays 0(sd)
begin
if(s#<b"") odA"C/
else if(s#<b"1) odA1C/
else if(s#<b1") odA#C/
else odA&C/
end
endmodule
Te"& be$c'
4timescale 1ns51ps
4include 6mu$b.6
module mu$1/
reg A&B"Cd8t/
reg A1B"Cs8t/
,ire o8t/
integer i/
mu$ m1(d8ts8to8t)/
initial
begin
9dumpfile(6mu$bdump.cd6)/
9dumpars(#mu$1.m1)/
end
initial
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begin
d8t<b"1"1/
for(i"/i=@/ii>1)
? :s8tA1Cs8tA"C;i/
end
initial
?1"" 9finis7/
ndmodule
b)de/ul&iple4er
De"i#$ /%dule
module dmu$(ysareset)/
input areset/
input A1B"Cs/
output regA&B"Cy/
al,ays 0(s)
begin
if (reset1<b")
begin
case (s)
#<b""Bbegin
yA"Ca/
yA1C"/
yA#C=0;
yA&C"/
end
#<b"1Bbegin
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
yA1Ca/
yA"C"/
yA#C"/
yA&C"/
end
#<b1"Bbegin
yA"C"/
yA1C"/
yA#Ca/
yA&C"/
end
defaultBbegin
yA"C"/
yA1C"/
yA#C"/
yA&Ca/
end
endcase
end
else
y&<b"""/
end
endmodule
Te"& be$c'
4timescale 1ns51ps
4include 6dmu$.6
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
module dmu$1/
reg a8treset8t/
reg A1B"Cs8t/
,ire A&B"Cy8t/
integer i/
dmu$ d1(y8ts8ta8treset8t)/
initial
begin
9dumpfile(6dmu$dump.cd6)/
9dumpars(#dmu$1.d1)/
end
initial
begin
a8t1<b1/
reset8t1<b1/
?1" reset8t1<b"/
for(i"/i=@/ii>1)
? :s8tA1Cs8tA"C;i/
end
initial
?1"" 9finis7/
endmodule
OBSERATIO*
a)/ul&iple4er
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
b)de/ul&iple4er
RESULT
7e L1 multiple$er and 1L demultiple$er 7as been designed and implemented and ,ae forms
7as been obtained.
Experiment No: 5
Date: 15 – 09 – 2011
0OH*SO* COU*TER A*D RI*G COU*TER
AIM
Design and implement Io7nson counter and Ring counter using Verilog code.
SOFTWARES USED
1. ModelSim (X 111 !."d)
#. Xilin$ (%.1i)
&. 'erilog
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
. *t+,ae
CIRCUIT DIAGRAM
a)0%'$"%$ c%u$&er
b)ri$# c%u$&er
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TRUTH TABLE
a)0%'$"%$ c%u$&er
b)ri$# c%u$&er
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ROGRAM
a)0%'$"%$ c%u$&er
De"i#$ /%dule
module Ko(cl+reset)/
reg A&B"C$/
input cl+reset/
output reg A&B"C/
al,ays0(posedge cl+)
if (reset1)
:$;%<b1"""1111/
else
(<b1""")N$==#B(<b11"")N$==1B(<b111")N$B(<b"""")N<b1"""B
OO1/
endmodule
Te"& be$c'
4timescale 1ns51ps
4include 6Ko7.6
module Ko71/
reg A&B"C$/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
reg cl+reset/
,ire A&B"C/
Ko K(cl+reset)/
initial
begin
9dumpfile(6KK.cd6)/
9dumpars(#Ko71.K)/
end
initial
begin
cl+1<b"/
reset1<b1/
?#" reset1<b"/
end
al,ays
?1" cl+Gcl+/
initial
?1""" 9finis7/
endmodule
b)Ri$# c%u$&er
De"i#$ /%dule
module ring1(cl+reset)/
input cl+reset/
output regA&B"C/
al,ays 0(posedge cl+)
if (reset1<b")
(A&CPA#CPA1C)NOO1B==&/
else
<b1"""/
endmodule
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Te"& be$c'
4timescale 1ns51ps
4include 6ring.6
module ringtb1/
reg cl+1reset1/
,ire A&B"C1/
ring1 r1(1cl+1reset1)/
initial
begin
9dumpfile (6ringdump.cd6)/
9dumpars (#ringtb1.r1)/
end
initial
begin
cl+11<b1/
reset11<b1/
?1" reset11<b"/
end
al,ays? cl+1Gcl+1/
initial
?1"" 9finis7/
endmodule
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
OBSERATIO*
a)0%'$"%$ c%u$&er
b)ri$# c%u$&er
RESULT
7e Io7nson counter and Ring counter 7as been designed and implemented and ,aeform
7as been obtained.
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Experiment No: 6
Date: 15 – 09 – 2011
ARALLEL I* SERIAL OUT SHIFT REGISTER
AIM
Design and implement parallel in serial out s7ift register using Verilog code.
SOFTWARES USED
1. ModelSim (X 111 !."d)
#. Xilin$ (%.1i)
&. 'erilog
. *t+,ae
CIRCUIT DIAGRAM
ROGRAM
De"i#$ /%dule
module piso(sorcpidir)/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
input dirrc/
input A&B"Cpi/
output reg so/
reg A&B"Ct/
integer count"/
al,ays 0(posedge c)
begin
if(r1)
begin
so1<b"/
t<b"/
end
else
begin
countcount>1/
case(dir)
1<b1Bcase(count)
1Btpi/
#BsotA"C/
&BsotA1C/
BsotA#C/
BsotA&C/
!Bcount"/
endcase
1<b"Bcase(count)
1Btpi/#BsotA&C/
&BsotA#C/
BsotA1C/
BsotA"C/
!Bcount"/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
endcase
endcase
end
end
endmodule
Te"& be$c'
4timescale 1ns51ps
4include 6piso.6
module piso8tb/
reg dir1r1c1/
reg A&B"Cpi1/
reg A&B"Ct/
,ire so1/
piso ps(so1r1c1pi1dir1)/
initial
begin
9dumpfile (6pisodump.cd6)/
9dumpars (#piso8tb.ps)/
end
initial
begin
c11<b1/
r11<b1/
dir11<b"/
pi1<b"/
?1" r11<b"/dir11<b1/
pi1<b"111/
?!" dir11<b"/
pi1<b11"1/
end
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
al,ays
begin
? c1Gc1/
end
initial
?"" 9finis7/
endmodule
OBSERATIO*
RESULT
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
7e program for parallel in serial out s7ift register ,as e$ecuted and output ,as erified ,
Experiment No: 7
Date: 16 – 09 – 2011
BARREL SHIFTER
AIM
Design and implement barrel s7ifter using Verilog code.
SOFTWARES USED
1. ModelSim (X 111 !."d)
#. Xilin$ (%.1i)
&. 'erilog
. *t+,ae
CIRCUIT DIAGRAM
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
ROGRAM
De"i#$ /%dule
module bs(sabcl+reset)/
input cl+reset/
input A#B"Cs/
input A&B"Ca/
output regA&B"Cb/
al,ays 0(posedge cl+)
begin
if(reset1<b")
bsA#CN(sA1CN(sA"CNaOOBaOO&)B(sA"CNaOO#BaOO1))B(sA1CN(sA"CNa==Ba==&)B(sA"CNa==#Ba==1))/
else
b<b""""/
end
endmodule
Te"& be$c'
4timescale 1ns51ps
4include 6barrl.6
module barreltb1/
reg cl+1reset1/
reg A#B"Cs1/
reg A&B"Ca1/
,ire A&B"Cb1/
integer i/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
barrel bs1(s1a1b1cl+1reset1)/
initial
begin
9dumpfile (6barreldump.cd6)/
9dumpars (#barreltb1.bs1)/
end
initial
begin
cl+11<b1/
reset11<b1/
a11<b"/
s11<b"/
?1" reset11<b"/
a1<b1"1"/
for(i"/i=@/ii>1)
?1" s1i/
end
al,ays
? cl+1Gcl+1/
initial
?1"" 9finis7/
ndmodule
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Experiment No: 8 Date: 19 – 09 – 2011
U*IERSAL SHIFT REGISTER
AIM
Design and implement uniersal s7ift register using Verilog code.
SOFTWARES USED
1. ModelSim (X 111 !."d)
#. Xilin$ (%.1i)
&. 'erilog
. *t+,ae
CIRCUIT DIAGRAM
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
'oll (o)10 41
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
'oll (o)10 42
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
ROGRAM
De"i#$ /%dule
module usr1(cl+resetmdsisopipo)/
input cl+resetsid/
input A1B"Cm/
input A&B"Cpi/
reg A&B"Ccount/
output reg A&B"Cpo/
output reg so/
reg A&B"Ct/
al,ays 0(posedge cl+)
begin
if (reset1)
begin
po<b"/
so1<b"/
count"/
t<b"/
end
else
begin
countcount>1/
case(m)
#<b""Bbegin
if (d")
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
begin
case(count)
<b"""1BtA"Csi/
<b""1"BtA1Csi/
<b""11BtA#Csi/
<b"1""BtA&Csi/
<b"1"1BsotA"C/
<b"11"BsotA1C/
<b"111BsotA#C/
<b1"""BsotA&C/
<b1""1Bcount<b""""/
endcase
end
else
begin
case(count)
<b"""1BtA"Csi/
<b""1"BtA1Csi/
<b""11BtA#Csi/
<b"1""BtA&Csi/
<b"1"1BsotA&C/
<b"11"BsotA#C/
<b"111BsotA1C/
<b1"""BsotA"C/
<b1""1Bcount<b""""/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
endcase
end
end
#<b"1Bbegin
case(count)
<b"""1BtA"Csi/
<b""1"BtA1Csi/
<b""11BtA#Csi/
<b"1""BtA&Csi/
<b"1"1Bpot/
<b"11"Bcount<b"/
endcase
end
#<b1"Bbegin
if (d")
begin
case(count)
<b"""1Btpi/
<b""1"BsotA"C/
<b""11BsotA1C/
<b"1""BsotA#C/
<b"1"1BsotA&C/
<b"11"Bcount<b"/
endcase
end
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
else
begin
case(count)
<b"""1Btpi/
<b""1"BsotA&C/
<b""11BsotA#C/
<b"1""BsotA1C/
<b"1"1BsotA"C/
<b"11"Bcount<b"/
endcase
end
end
#<b11Bbegin
case(count)
<b"""1Btpi/
<b""1"Bpot/
<b""11Bcount<b"/
endcase
end
endcase
end
end
endmodule
Te"& be$c'
4timescale 1ns51ps
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
4include 6usr.6
module usrtb1/
reg cl+1reset1si1d1/
reg A1B"Cm11/
reg A&B"Cpi1/
,ire so1/
,ire A&B"Cpo1/
usr1 u1(cl+1reset1m11d1si1so1pi1po1)/
initial
begin
9dumpfile(6usrdump.cd6)/
9dumpars (#usrtb1.u1)/
end
initial
begin
cl+11<b1/
reset11<b1/
pi1<b"/
?1" reset11<b"/
m11#<b""/
d11<b1/
si11<b1/
?1" si11<b1/
?1" si11<b"/
?1" si11<b1/
'oll (o)10 47
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
?!" m11#<b"1/
si11<b1/
?1" si11<b1/
?1" si11<b"/
?1" si11<b1/
?" m11#<b1"/
d11<b"/
pi1<b1"11/
?!" m11#<b11/
pi1<b1"11/
end
al,ays
? cl+1Gcl+1/
initial
?1""" 9finis7/
endmodule
OBSERATIO*
'oll (o)10 48
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
RESULT
Qniersal s7ift register 7as been designed and implemented and ,ae form 7as been
obtained ,
'oll (o)10 49
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Experiment No: 9
Date: 20 – 09 – 2011
COMARATOR
AIM
Design and implement comparator using Verilog code.
SOFTWARES USED
1. ModelSim (X 111 !."d)
#. Xilin$ (%.1i)
&. 'erilog
. *t+,ae
CIRCUIT DIAGRAM
'oll (o)10 50
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
TRUTH TABLE
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
ROGRAM
De"i#$ /%dule
module compr(yab)/
input A#B"Ca/
input A#B"Cb/
output A#B"Cy/
assign y(ab)N1""B((a=b)N"1"B""1)/
endmodule
Te"& be$c'
`timescale 1ns/1ps
`include "comp.v"
module comp1;
e! 2#0$a1;
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
e! 2#0$%1;
&ie 2#0$';
comp c(')a1)%1*;
initial
%e!in
+dump,ile("compdump.vcd"*;
+dumpvas(2)comp1.c*;
end
initial
%e!in
a1=3-%001;
%1=3-%010;
5
a1=3-%000;
%1=3-%000;
5
a1=3-%011;
%1=3-%001;
end
initial
100 +,inis;
endmodule
OBSERATIO*
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
RESULT
7e comparator circuit 7as been designed and implemented and ,ae forms 7as been obtained.
Experiment No: 10
Date: 20– 09 – 2011
UDOW* COU*TER
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
AIM
Design and implement updo,n counter using Verilog code.
SOFTWARES USED
1. ModelSim (X 111 !."d)
#. Xilin$ (%.1i)
&. 'erilog
. *t+,ae
CIRCUIT DIAGRAM
56 5+
5-
789
mode
Eloc+
'oll (o)10 55
0
0
0
1
1
1
2
2
2
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
TRUTH TABLE
C%u$&er "&a&e"
re"e$& "&a&e *e4& "&a&e
M%de 5- 5+ 56 5- 5+ 56
" " " " " " 1
" " " 1 " 1 "
" " 1 " " 1 1
" " 1 1 1 " "
" 1 " " 1 " 1
" 1 " 1 1 1 "
" 1 1 " 1 1 1
" 1 1 1 " " "
1 1 1 1 1 1 "
1 1 1 " 1 " 1
1 1 " 1 1 " "
1 1 " " " 1 1
1 " 1 1 " 1 "
1 " 1 " " " 1
1 " " 1 " " "
1 " " " 1 1 1
ROGRAM
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
De"i#$ bl%c:
module updo&n1(out)m)cl)eset*;
input cl)eset)m;
output e! 3#0$out;
al&as (ne!ed!e cl*
%e!in
i, (eset==1*
out=3-%000;
else
%e!in
case(m*
1-%0#out=out1;
de,ault#out=out1;
endcase
end
end
endmodule
Te"& be$c'
`timescale 1ns/1ps
`include "updo&n.v"
module updo&nt%1;
e! mt)clt)esett;
&ie 2#0$outt;
updo&n1 ud(outt)mt)clt)esett*;
initial
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
%e!in
+dump,ile("updo&ndump.vcd"*;
+dumpvas(2)updo&nt%1.ud*;
end
initial
%e!in
clt=1-%1;
esett=1-%1;
10 esett=1-%0;
mt=1-%1;
40 mt=1-%0;
end
al&as
5 clt=:clt;
initial
200 +,inis;
ndmodule
OBSERATIO*
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
RESULT
7e program for updo,n counter ,as e$ecuted and output ,as erified
Experiment No: 11
Date: 21 – 09 – 2011
DECADE COU*TER
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
AIM
Design and implement decade counter using Verilog code.
SOFTWARES USED
1. ModelSim (X 111 !."d)
#. Xilin$ (%.1i)
&. 'erilog
. *t+,ae
CIRCUIT DIAGRAM
TRUTH TABLE
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Ou&pu&"
Cl%c: 5A 5B 5C 5D
" " " " "
1 " " " 1
# " " 1 "
& " " 1 1
" 1 " "
" 1 " 1
! " 1 1 "
@ " 1 1 1
% 1 " " "
1 " " 1
ROGRAM
De"i#$ /%dule
module mod1"1(outcl+reset)/
input cl+reset/
output regA&B"Cout/
al,ays 0(posedge cl+)
begin
if (reset1)
out<b""""/
else
begin
if (out=<b1""1)
outout>1/
else
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
out<b""""/
end
end
endmodule
Te"& be$c'
4timescale 1ns51ps
4include 6mod1".6
module mod1"tb1/
reg cl+8treset8t/
,ire A&B"Cout8t/mod1"1 m1"(out8tcl+8treset8t)/
initial
begin
9dumpfile(6mod1"dump.cd6)/
9dumpars(#mod1"tb1.m1")/
end
initial
begin
cl+8t1<b1/
reset8t1<b1/
?1" reset8t1<b"/
end
al,ays
? cl+8tGcl+8t/
initial
?#"" 9finis7/
endmodule
OBSERATIO*
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
RESULT
7e circuit for decade counter 7as been designed and implemented and
,aeforms 7as been obtained.
Experiment No: 12
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Date: 21 – 09 – 2011
SE5UE*CE DETECTOR
AIM
Design and implement seuence detector ("111") using Verilog code.
SOFTWARES USED
1. ModelSim (X 111 !."d)
#. Xilin$ (%.1i)
&. 'erilog
. *t+,ae
CIRCUIT DIAGRAM
'oll (o)10 64
<
>
1/0
1/01/0
0/0
1/0
1/0
0/1
0/0
0/0
0/0
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
TRUTH TABLE
ROGRAM
De"i#$ /%dule
module se1($cl+reset)/
input $cl+reset/
output reg /
reg A#B"Cns/
reg A#B"Cps/
al,ays 0(posedge cl+)
begin
if (reset1<b")
begin
if ($1)
begincase(ps)
&<b"""Bbegin
ns&<b""1/
1<b"/
ps&<b""1/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
end
&<b""1Bbegin
ns&<b"1"/
1<b"/
ps&<b"1"/
end
&<b"1"Bbegin
ns&<b"11/
1<b"/
ps&<b"11/
end
&<b"11Bbegin
ns&<b1""/
1<b"/
ps&<b1""/
end
&<b1""Bbegin
ns&<b1""/
1<b"/
ps&<b1""/
end
endcase
end
else
begin
case(ps)&<b"""Bbegin
ns&<b"""/
ps&<b"""/
1<b"/
end
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
&<b""1Bbegin
ns&<b"""/
ps&<b"""/
1<b"/
end
&<b"1"Bbegin
ns&<b"""/
ps&<b"""/
1<b"/
end
&<b"11Bbegin
ns&<b"""/
ps&<b"""/
1<b1/
end
&<b1""Bbegin
ns&<b"""/
ps&<b"""/
1<b"/
end
endcase
end
end
else
begin
1<b"/ns&<b"/
ps&<b"/
end
end
endmodule
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Te"& be$c'
4timescale 1ns51ps
4include 6se#.6
module se#tb1/
reg cl+1reset1/
reg $1/
,ire 1/
se1 s1($11cl+1reset1)/
initial
begin
9dumpfile (6sedump.cd6)/
9dumpars (#se#tb1.s1)/
end
initial
begin
cl+11<b1/
reset11<b1/
?1" reset11<b"/
$11<b"/
?1" $11<b1/
?1" $11<b1/
?1" $11<b1/
?1" $11<b"/
?1" $11<b1/
?1" $11<b1/
?1" $11<b1/
?1" $11<b1/
?1" $11<b"/
?1" $11<b1/
?1" $11<b1/
'oll (o)10 68
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
?1" $11<b1/
?1" $11<b"/
?1" $11<b1/
?1" $11<b"/
end
al,ays
? cl+1Gcl+1/
initial
?#"" 9finis7/
endmodule
OBSERATIO*
RESULT
7e circuit for seuence detector 7as been designed and implemented and
,aeforms 7as been obtained.
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Experiment No: 13
Date: 23– 09 – 2011
ALU
AIM
Design and implement -TQ using Verilog code.
SOFTWARES USED
1. ModelSim (X 111 !."d)
#. Xilin$ (%.1i)
&. 'erilog
. *t+,ae
CIRCUIT DIAGRAM
ROGRAM
De"i#$ /%dule
module alu($ymout1out#cl+reset)/
input A#B"C$/
input A#B"Cy/
input A1B"Cm/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
input cl+reset/
output reg A&B"Cout1/
output reg A&B"Cout#/
al,ays 0(posedge cl+)
begin
if(reset")
begin
case(m)
#<b""B:out1out#;$>y/
#<b"1B:out1out#;$Uy/
#<b1"B:out1out#;$Ly/
defaultB:out1out#;$5y/
endcase
end
else
:out1out#;%<b"/
end
endmodule
Test bench
4timescale 1ns51ps
4include 6alu.6
module alu1tb/
reg A#B"C$1/
reg A#B"Cy1/
reg A1B"Cm1/
reg cl+1reset1/
,ire A&B"Cout11/
,ire A&B"Cout#1/
alu a1($1y1m1out11out#1cl+1reset1)/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
initial
begin
9dumpfile(6aludump.cd6)/
9dumpars(#alu1tb.a1)/
end
initial
begin
reset11<b1/
cl+11<b1/
m1#<b""/
$1&<b"""/
y1&<b"""/
?1" reset11<b"/
cl+11<b1/
$1&<b1""/
y1&<b"1"/
m1#<b""/
?#" m1#<b"1/
?#" m1#<b1"/
?#" m1#<b11/
end
al,ays
? cl+1Gcl+1/
initial
?#"" 9finis7/
endmodule
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
OBSERATIO*
RESULT
7e circuit for -TQ 7as been designed and implemented and ,aeforms 7as been obtained .
'oll (o)10 73
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Experiment No:14
Date: 23 – 12 – 2011
( WA; TRAFFIC LIGHT S;STEM
AIM
<esi!n and implement a 4 &a ta,,ic li!t sstem usin! ?eilo! code.
SOFTWARES USED
1. ModelSim (X 111 !."d)
#. Xilin$ (%.1i)
&. 'erilog
. *t+,ae
CIRCUIT DIAGRAM
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
ROGRAM
De"i#$ /%dule
module traffic(p1p#p&pcr)/
output reg A#B"Cp1/
output reg A#B"Cp#/
output reg A#B"Cp&/
output reg A#B"Cp/
input cr/
integer d"/
al,ays 0(negedge c)
begin
if(r1<b1)
begin
p1&<b1""/
p#&<b1""/ p&&<b1""/
p&<b1""/
end
else
begin
dd>1/
case(d)
1B
begin
p1&<b""1/
p#&<b1""/
p&&<b1""/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
p&<b1""/
end
B
begin
p1&<b"1"/
p#&<b1""/
p&&<b1""/
p&<b1""/
end
@B
begin
p1&<b1""/
p#&<b""1/
p&&<b1""/
p&<b1""/
end
11B
begin
p1&<b1""/
p#&<b"1"/
p&&<b1""/
p&<b1""/
end
1&B begin
p1&<b1""/
p#&<b1""/
p&&<b""1/
p&<b1""/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
end
1@B
begin
p1&<b1""/
p#&<b1""/
p&&<b"1"/
p&<b1""/
end
1B
begin
p1&<b1""/
p#&<b1""/
p&&<b1""/
p&<b""1/
end
#&B
begin
p1&<b1""/
p#&<b1""/
p&&<b1""/
p&<b"1"/
end
#B
begin
p1&<b1""/ p#&<b1""/
p&&<b1""/
p&<b1""/
end
endcase
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
end
end
endmodule
Te"& be$c'
4timescale 1ns51ps
4include 6traffic.6
module traffic8tb/
reg c1r1/
,ire A#B"Cp11/
,ire A#B"Cp#1/,ire A#B"Cp&1/
,ire A#B"Cp1/
traffic tr(p11p#1p&1p1c1r1)/
initial
begin
9dumpfile (6trafficdump.cd6)/
9dumpars (#traffic8tb.tr)/
end
initial
begin
c11<b"/
r11<b1/
? r11<b"/
end
al,ays
? c1Gc1/
initial
?"" 9finis7/
'oll (o)10 78
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
endmodule
OBSERATIO*
RESULT
- ,ay traffic lig7t controller 7as been designed and implemented
,aeforms 7ae been obtained.
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
Experiment No:15
Date: 24– 12 – 2011
RAM
AIM
<esi!n and implement a @A usin! ?eilo! code.
SOFTWARES USED
1. ModelSim (Versions)
#. Xilin$ (Versions)
&. 'erilog
. *t+,ae
CIRCUITDIAGRAM
TRUTH TABLE
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
ROGRAM
De"i#$ /%dule
module ram1(dindoutreaddrcl+)/
input ercl+/
input A&B"Caddr/
input A@B"Cdin/
output reg A@B"Cdout/
reg A@B"CmemA1B"C/
al,ays 0(posedge cl+)
begin
if (e1)
begin
case(r)
1<b"BdoutmemAaddrC/
1<b1Bbegin
memAaddrCdin/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
dout%<b"/
end
endcase
end
else
begin
memA<b"""1C%<b"""""111/
memA<b""1"C%<b"/
dout%<b"/
end
end
endmodule
Te"& be$c'
4timescale 1ns51ps
4include 6ram.6
module ramtb1/
reg cl+1e1r1/
reg A&B"Caddr1/
reg A@B"Cdin1/
reg A@B"CmemA1B"C/
,ire A@B"Cdout1/
ram1 rr1(din1dout1r1e1addr1cl+1)/
initial
begin
9dumpfile (6ramdump.cd6)/
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
9dumpars (#ramtb1.rr1)/
end
initial
begin
cl+11<b1/
e11<b"/
addr1<b"/
din11<b"/
r11<b"/
?1" e11<b1/
r11<b"/
addr1<b"""1/
din1%<b"/
?1" r11<b1/
din1%<b""""11""/
addr1<b"1"1/
?1" r11<b"/
addr1<b"1"1/
din1%<b"/
end
al,ays
? cl+1Gcl+1/
initial
?1"" 9finis7/
endmodule
'oll (o)10 83
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Department of Electronics and Communication EngineeringLMV 108 – VLSI Design Lab Viswa!ot"i College of Engineering and #ec"nolog!$Va%"a&ulam
OBSERATIO*
RESULT
- R-M 7as been designed and implemented and ,aeforms 7ae been obtained.