GIF-4201/GEL-7016 (Micro-électronique)

Lab 3: FPGA and VLSI Design VHDL code, synthesis, design verification

Gabriel Gagnon-Turcotte, Mehdi Noormohammadi Khiarak and Benoit Gosselin

Department of Electrical & Computer Engineering

Laval University, Quebec City, Canada

February 2018

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Version history

Version Description Authors Date

1 Original revision G. Gagnon-Turcotte, M.

Noormohammadi Khiarak and Benoit Gosselin

Feb. 23 2018

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Introduction 3

Objectives of this Lab 3

VHDL language references 3

VHDL basics 4

Libraries and packages 4

Entity & ports 4

Architectures 6

Concurrent signal assignment 6

Entities inside architectures 7

Creating a project with Xilinx ISE 13

Creation of a test bench and behavioral simulation with ISim 18

Post-Route simulation with ISim 24

Pipelined adder 26

How to launch Modelsim 31

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Introduction

A field-programmable gate array (FPGA) device can be seen as an ocean of logic components that can be interconnected together to create complex digital circuits. They are well suited for high speed applications, complex signal processing or high speed control. In the first steps, FPGA and CMOS digital circuits are designed the same way, by using either Verilog or Very High speed Integrated Circuit Hardware Description Language (VHDL) code. Note: this lab will focus on VHDL only.

This lab exercises will guide you through mastering VHDL design, test bench design, synthesis and simulations. The teaching assistant (TA) will assist you in the PLT-0105 during the time period assigned to this practical work.

Objectives of this Lab

This third lab will give you an introduction to the VHDL language, to the numeric design using VHDL, and to the creation of test bench. This lab is performed using ISE software from Xilinx at the Department of Electrical and Computer Engineering, Laval University, computer Lab PLT-0105.

In the first part of this lab, you will learn the basics of the VHDL language. Secondly, you will learn how to create a project in ISE and to synthesize a combinational adder for a FPGA platform. Then, in the second part, you will learn how to create test benches and to use input-output capabilities of the VHDL language. Finally, in the third part, you will implement a pipelined adder and compare its performances with it's combinational counterpart.

VHDL language references

WESTE et HARRIS, Principles of CMOS VLSI design, 4th edition. Addison-Wesley, 2010.

Site web: http://pages.hmc.edu/harris/cmosvlsi/4e/index.html

VHDL for beginners:

https://www.nandland.com/vhdl/tutorials/tutorial-introduction-to-vhdl-for-beginners.html

VHDL Tutorial: U. Chicago, Peter J. Ashenden:

http://hep.uchicago.edu/~tangjian/SVT_sub/FTK_ATLAS/AUX/vhdl-tutorial.pdf

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VHDL basics

Like almost all typical languages, the structure of VHDL provides an external interface (prototype/entities) and an implementation (architecture). A VHDL design consists of entities, architectures and configurations/instantiations.

Libraries and packages

The first step when creating a VHDL file is to include the name of the libraries that will be used. This is done using this syntax:

library IEEE;use ieee.std_logic_1164.all;use ieee.numeric_std.all;

The above example shows how to use the ieee library with the std_logic_1164 and numeric_std packages. Among others, the std_logic_1164 package includes the basic declarations, like std_logic, std_logic_vectors, rising_edge/falling_edge, while the numeric_std package includes the declaration of more sophisticated types like unsigned, signed and their respective arithmetic operations. However, be aware that the physical implementation of the numeric_std package is not optimized for any intended application. So, it is common to implement manually some operations or types included in the numeric_std package, like additions, to optimize the speed and/or the area of the circuit.

Entity & ports

The next step is to create the module entity, which declares the design's interface. A typical entity declaration is shown as follow:

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entity entity_name is generic( generic_name_1 : generic_type_1; generic_name_2 : generic_type_2; generic_name_n : generic_type_n ); port( port_name_1 : port_dir_1 port_type_1; port_name_2 : port_dir_2 port_type_2; port_n_name_n : port_dir_n port_type_n ); end entity_name;

Here, the generic keyword is optional, and is used to create instance-specific parameters. The port keyword allows to define the inputs/outputs of the module. The port_dir_x can be set to in, out, inout, buffer, etc. Note: a in signal can be read but not written inside the entity, a out signal cannot be read inside the entity but can be written, a inout and buffer can be both read and written inside the entity. The entity of a simple XOR gate is shown as follow:

entity xor_gate isport( A_in : in std_logic; B_in : in std_logic; C_out : out std_logic);end xor_gate;Equivalent schematic:

Entity

Architecture

A_in

B_inC_out

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Unlike typical coding languages, the VHDL language is used to process signals, not variables (variables can be declared in VHDL, but we forbid their utilization in either FPGA or CMOS designs because they are hard to synthesize i.e not synthesizable). Don't forget that your code will be implemented physically using transistors and metal layers. In the above example, the keyword std_logic indicates a type that represents a one bit physical signal. It can take values like '1', '0' or 'Z'. Another type representing a "bus" is the std_logic_vector type. This type can be declared using this syntax: std_logic_vector (max downto min), where max and min fix the boundaries of the bus. Each element inside a std_logic_vector is of type std_logic.

Architectures

The architecture contains the internal implementation of the entity. Multiple architectures can be created for the same entity, which can have different performances or behavior. For instance, each architecture can be optimized for: speed, area, power consumption or simulation. An architecture is defined as follow:

ARCHITECTURE architecture_name OF entity_name IS -- internal signal declaration -- entity declaration (if required) BEGIN -- entity instantiation (if required) -- VHDL code END architecture_name;

The following is an example of architecture for the XOR gate:

ARCHITECTURE xor_gate_arch OF xor_gate IS signal not_A_in: std_logic; signal not_B_in: std_logic; BEGIN not_A_in <= not(A_in); not_B_in <= not(B_in); C_out <= (not_A_in and B_in) or (not_B_in and A_in); END xor_gate_arch;

In the last example, and, or and not are operations on the std_logic types that are already defined in the std_logic_1164 package.

Concurrent signal assignment

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In a concurrent statement, the symbol "<=" means to connect (or assign) a signal to another one. Everything inside an architecture that is not inside a process is considered as a concurrent statement (processes will be covered later in this lab). In VHDL, it is also possible to design conditional assignments. The following shows 2 ways of doing conditional assignments:

-- ... Entity ...ARCHITECTURE conditional_test_arch OF conditional_test IS SIGNAL a, b, c, d, e :std_logic; SIGNAL a_select :std_logic_vector(1 DOWNTO 0); SIGNAL b_select :std_logic_vector(2 DOWNTO 0);BEGIN -- ... code ... -- Conditional Assignment Statement a <= '0' WHEN a_select = "00" ELSE b WHEN a_select = "11" ELSE c; -- Selected Signal Assignment Statement b_select <= d & a_select; WITH b_select SELECT e <= '0' WHEN "000", b WHEN "011", c WHEN "100", '1' WHEN OTHERS; -- ... code ...END conditional_test_arch;

In this example, the value of a is determined by the signal a_select. The value of e is determined by d concatenated to a_select. Indeed, the operator & can be used to concatenate two std_logic_vector together or one std_logic_vector with an std_logic. Note, with a conditional assignment, all the possible cases need to be covered. For that reason, the use of statements else or other is required for synthesis (most of the time).

Entities inside architectures

Complex designs often require to instantiate entities inside architecture. Suppose the following inverter module:

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library IEEE;use IEEE.STD_LOGIC_1164.ALL; entity inverter isport( A_in : in std_logic; B_out : out std_logic);end inverter; architecture inverter_arch of inverter isbegin B_out <= '0' WHEN A_in = '1' ELSE '1';end inverter_arch;

Now, we can reuse this inverter entity inside the XOR architecture this way:

ARCHITECTURE xor_gate_arch OF xor_gate IS signal not_A_in: std_logic; signal not_B_in: std_logic; -- Entity declaration component inverter port( A_in : in std_logic; B_out : out std_logic ); end component; BEGIN -- Entity instantiation inverter_inst_1: inverter port map ( A_in => A_in, B_out => not_A_in ); -- Entity instantiation inverter_inst_2: inverter port map ( A_in => B_in, B_out => not_B_in ); C_out <= (not_A_in and B_in) or (not_B_in and A_in); END xor_gate_arch;

First, the entity is declared in the signal declaration section (before the begin keyword) and the instances are created in the code section (after the begin keyword).

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Answer these questions in your report:

Q1: Create the AND & OR modules and reuse them to re-create the XOR module. You cannot use the keyword AND, OR, NOT & XOR. Put all the code in your report. Tip: for AND & OR modules, concatenate the inputs to form a 2-bit std_logic_vector and use it in a conditional assignment that covers the whole truth table.

Process

In VHDL, a process encapsulates a portion of design that has to be executed at specific events only, like clock edge. For that reason, all processes have a sensitivity list that specifies the signals that triggers changes in the output of the process. Among others, the sensitivity list can be used to preserve the state of the signals using memory elements (D flip-flop, latch, etc.). The concurrent statement seen before has their equivalents inside a process:

Concurrent Inside process when...else If...elsif...else...end if

With...select...when Case...when...end case

Here is a simple process that implements a D flip-flop with an active high reset:

-- ... Code ...signal rst, clk, A_in, B_out;begin -- ... Code ... process(rst, clk) if(rst = '1') then --rst active high B_out <= '0'; elsif(clk'event and clk = '1') then --clk rising edge B_out <= A_in; end if; end process;end D_flip_flop

If the state of rst is changed to '1', the signal B_out is reset to '0', otherwise, if the clk signal goes from any value to '1', the signal A_in is assigned to B_out. It is very important to understand that the updated value will not be available until the next rising edge of clk. This is because the physical implantation of a process will be done using clocked memory units (D flip-flop, latch, etc.) that are all updated at the same time, not sequentially. This can be seen in the following code:

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-- ... Code ... signal rst, clk, A_in, B_out, B_out_buffer; begin -- ... Code ... process(rst, clk) if(rst = '1') then --rst active high B_out <= '0'; B_out_buffer <= '0'; elsif(clk'event and clk = '1') then --clk rising edge B_out_buffer <= A_in; B_out <= B_out_buffer; end if; end process; end D_flip_flop

Upon the rising edge of clk, A_in is assigned to B_out_buffer, while the previous value of B_out_buffer is assigned to B_out. Doing so, there is a latency of 1 clock cycle before A_in is reflected to B_out. This behaviour is not intuitive, and contrasts with sequential coded language behavior.

Using processes, it is possible to create state machines. This is usually done using the case statement in a process that will execute the code according to the current value of the signal that is used in the statement. Note: multiple state machines can be implemented inside the same architecture and processes and they will be processed in parallel. The following example shows a simple state machine that controls two lights according to the state of 2 buttons:

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library ieee;use ieee.std_logic_1164.all; entity light_machine is port( rst : in std_logic; en : in std_logic; clk : in std_logic; buttons : in std_logic_vector(1 downto 0); lights : out std_logic_vector(1 downto 0) );end light_machine; architecture light_machine_arch of light_machine is type statetype is (idle, st1, st2, error); signal currentstate : statetype;begin finite_state_machine: process(rst, clk) if (rst = '0') then currentstate <= idle; elsif clk'event and clk = '1' and en = '1' then begin case currentstate is when idle => lights <= "00"; case buttons is when "00" => currentstate <= idle; when "01" => currentstate <= st1; when "10" => currentstate <= st2; when others => currentstate <= error; end case; when st1 => lights <= "01"; if buttons /= "01" then currentstate <= idle; end if; when st2 => lights <= "10"; if buttons /= "10" then currentstate <= idle; end if; when error => lights <= "11"; if buttons = "00" then currentstate <= idle; end if; end case; end if; end process;

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As seen above, it is possible to create new types using the following syntax: type new_type_name is type_definition. This feature is useful to give name for each state inside a stage machine, but also to create complex type. Ex: type word is array (0 to 31) of bit.

Q2: Design a 7-segment display controller, like presented in Figure 1. Put the VHDL code in your report.

VHDL module

Binary_numberstd_logic_vector(2 downto 0)

7 segment controlstd_logic_vector(6 downto 0)

Figure1.VHDLcombinationalmoduletocontrola7-segmentdisplay.

Q3: Reuse the 7-segment display controller of Q2 to display the incremental value of a counter, like presented in Figure 2. The counter has to be incremented at each clock cycle. Tips: use the ieee.numeric_std package and the unsigned type.

VHDL module

clk 7 segment controlstd_logic_vector(6 downto 0)

rst

en

Figure2.VHDLsequentialmoduletocontrola7-segmentdisplay.The7-segmentdisplayshowsthevalueofacounterincrementedateachclockcycles.

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Creating a project with Xilinx ISE

Designing VHDL modules for CMOS implementation using the online tools from CMC can be slow and frustrating. For that reason, we recommend to code and simulate your design using IDE already available for FPGA. It is important to note that these tools are well suited for early design stages because they allow to simulate and debug your circuit at the behavioral level. However, these tools are not well suited to simulate the CMOS gate level implementations, which topic will be covered in the laboratory 4.

In this section, you will create a Xilinx project containing a VHDL module that performs the addition of two 6-bit numbers with combinatory logic. Then, you will synthesize it and check it's performances using the Spartan-6 FPGA.

Step 1. Open the Xilinx ISE Design suite.

Step 2. Select File->New Project...

Step 3. Fill the name box with combinationnalAdder, select the location to save the project. Make sure the "Top-level source type" is set to HDL. Select "Next".

Step 4. For the family, select Spartan 6, for device select XC6SLX9, for package select tqg144.. Make sure the preferred language is set to VHDL. Select "Next" and then "Finish". Note: the FPGA model is not relevant, but we need this configuration to create the project. Also, we want all the students to select the same model so the timing constraints will be the same for everyone.

Step 5. Your IDE should look like Figure 3.

Step 6. Right click in the "Empty View" section and select "New source...". In the "New Source Wizard", select "VHDL Module" and write combinationnalAdder as the "File name", select "Next".

Step 7. Fill the "New Source Wizard" window as shown in Figure 4 and select "Next" and then "Finish".

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Step 8. The IDE will automatically create a file that includes the basic IEEE library, the entity and the architecture template. To be able to compute the propagation delay of the combinational circuit that you will design, you need to add two processes, as shown in Figure 5. Modify the template so it looks like in Figure 5.

Step 9. Implements in the missing section (combinational part) of the template of Figure 5 to perform the addition. A binary addition mainly consists of cascading one half adder with full adders. The circuit you have to implement is presented in Figure 6. Note: you can use all the built-in logic operations (not, or, xor, etc.), but no additions shall be used. Provide your VHDL code in your report.

Step 10. Once the VHDL design is implemented, expand the "User Constraints" in the "Processes" tab. Double click on "I/O Pin Planning (PlanAhead) - Pre-Synthesis". The software " PlanAhead " will open, fill the site section for each pins as is Figure 7. Save and close PlanAhead. Note: PlanAhead is a software that allows to configure the physical pinout of your design. Each port of your top entity has to be assigned to a dedicated pin. Furthermore, this software allows to configure the pins, like to add pull-up or pull-down or to configure the current strength of the output pins. Finally, the same configuration can be made manually by editing the .ucf file in your workspace without using PlanAhead.

Step 11. In the "Processes" tab, double click on "Implement Design". The synthesizing of your design can take 1-2 minutes. If there is no error in your VHDL code, you should see "Process "Generate Post-Place & Route Static Timing" completed successfully " when the synthesizing is finished.

Step 12. In the IDE console, locate the maximum frequency achievable by your design. Put a screenshot of the console output indicating this value in your report.

Q4: Considering the maximum clock frequency of the spartan-6 can be > 1GHz, what is the main limiting factor of the speed of your circuit?

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Figure3.EmptyprojectusingISE.

Figure4.Entitypinoutassignment.

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library ieee;use ieee.std_logic_1164.all; entity combinationnalAdder is Port ( clk : in STD_LOGIC; rst : in STD_LOGIC; op_a : in STD_LOGIC_VECTOR (5 downto 0); op_b : in STD_LOGIC_VECTOR (5 downto 0); op_ready: in STD_LOGIC; result : out STD_LOGIC_VECTOR (6 downto 0); result_ready : out STD_LOGIC); end combinationnalAdder; architecture combinationnaladder_arch of combinationnalAdder is signal op_ready_b : std_logic; signal result_b: std_logic_vector(6 downto 0); signal op_a_b : std_logic_vector(5 downto 0); signal op_b_b : std_logic_vector(5 downto 0); begin --add combinationnal logic to perform here set_operand_process: process(clk, rst) --To properly calculate the propa-gation delay begin if rst = '1' then op_ready_b <= '0'; op_a_b <= (others => '0'); op_b_b <= (others => '0'); elsif (clk'event and clk = '1') then if op_ready = '1' then op_a_b <= op_a; op_b_b <= op_b; end if; op_ready_b <= op_ready; end if; end process; output_result_process: process(clk, rst) --To properly calculate the propagation delay begin if rst = '1' then result <= (others => '0'); elsif (clk'event and clk = '1') then result <= result_b; result_ready <= op_ready_b; end if; end process; end combinationnaladder_arch ;

Figure5.TemplateforthecombinationnalAddermodule.

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ABS

C

ABS

C

Ci

ABS

C

Ci

ABS

C

Ci

ABS

C

Ci

ABS

C

Ci

A0B0 R0 A1B1 A2B2

A3B3 A4B4 A5B5

R1 R2

R3 R4 R5

Half adder

Full adder Full adder

Full adder Full adder Full adder

Q

QSET

CLR

D

rst

clkOp_b Op_b_buffer

(B0 .. B5)

Q

QSET

CLR

D

rst

clkOp_a Op_a_buffer

(B0 .. B5)

Q

QSET

CLR

D

rst

clkResultResultBuffer

(R0-R6)

ABS

Ci

A5B5 R6

Sign bit

Figure6.6-bitadderusingonehalfadderand5fulladders.

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Figure7.PlanAheadpinsconfiguration.

Creation of a test bench and behavioral simulation with ISim

In the previous part of this lab, we went through the VHDL coding of a simple 6-bit adder. In this section, we will continue this process and create a test bench to validate the behavioral functioning of this design. A behavioral simulation allows to verify the logic of your VHDL code, without any timing, fan-in/out, routing or other physical constraints.

Step 1. Using ISE, Xilinx makes it simple to create a test bench template. In the design section, set "View" to "Simulation". Then, right click in the "Hierarchy" section and select "New source...".

Step 2. In the "New source Wizard" window, select "VHDL Test Bench" and give the name combinationnalAdder_TB. Then, click "Next" twice and "Finish". Automatically, ISE should create a template containing the instantiation of the combinationnalAdder entity, a "clk_process" and a "stim_proc" processes. By default, the clock period is of 10 ns.

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Step 3. In this test bench, you will have to read and write files. To do that you need to add a file to your project. In the "Hierarchy" section, select "Add Copy of source..." and select the file " txt_util.vhd" provided with this lab, and click "OK" in the pop-up window.

Step 4. Modify the template so it looks like Figure 8. It is important to note that a test bench is executed differently than in a typical VHDL instance. Some mnemonics are not synthesizable, however they are useful in simulation. For example, "wait for xx" is not synthesizable but can be used in a test bench. Also, for a process inside a test bench, the simulator will execute all the lines of codes before a "wait" statement in parallel, like it is done in a typical VHDL code. However, after the "wait" statement the values previously assigned are updated. Carefully look at the test bench code to understand how it works.

Step 5. Add the missing code in, and after, the "stim_proc" process to provide the stimulation inputs to the combinationnalAdder instance. Note: use the 6 msb of y_op_a and y_op_b .

Step 6. Make sure the files "op_a.dat", "op_b.dat" and "combinationnalAdder_custom.prj" are in your project workspace.

Step 7. Expand the "ISim Simulator" tab. Make sure that "combinationnalAdder_TB" is selected in the Hierarchy section. Right click on "Simulate Behavioral model" and select "Process Properties...". Set the "Simulation Run Time" to 100000 ns and click "OK". Then, right click on "Simulate Behavioral model" and select "Run".

Step 8. Check the console output, if there is any error in your code, fix them. Otherwise, the ISim simulator window will open. It should look like Figure 9.

Step 9. Right click in the simulation window, i.e. where the green signals are displayed, and select "To Full View". The whole temporal simulation should be displayed. At the right of the temporal simulation, all the signals of the test bench are displayed. Right click on op_a[5:0], and select Radix->Signed Decimal. Do the same for op_b[5:0] and result[6:0].

Step 10. In the temporal simulation, click toward the 2 µs time. A yellow vertical line will appear. Then, hold "ctrl" and roll your mouse wheel to zoom in or out. Zoom enough to make the results visible and provide a print screen in your report. You can also check the test bench results in the "result.dat" file produced by the simulation.

Q5: Put the content of result.dat in your report.

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library ieee; use ieee.std_logic_1164.all; ----- add here ----- use ieee.numeric_std.all; library work; use work.txt_util.all; library std; use std.textio.all; -------------------- entity combinationnaladder_tb is end combinationnaladder_tb; architecture behavior of combinationnaladder_tb is -- component declaration for the unit under test (uut) component combinationnaladder port( clk : in std_logic; rst : in std_logic; op_a : in std_logic_vector(5 downto 0); op_b : in std_logic_vector(5 downto 0); op_ready: in std_logic; result : out std_logic_vector(6 downto 0); result_ready : out std_logic ); end component; --inputs signal clk : std_logic := '0'; signal rst : std_logic := '0'; signal op_ready: std_logic := '0'; signal op_a : std_logic_vector(5 downto 0) := (others => '0'); signal op_b : std_logic_vector(5 downto 0) := (others => '0'); --outputs signal result : std_logic_vector(6 downto 0); signal result_ready : std_logic; ----- change here ----- -- clock period definitions constant clk_period : time := 100 ns; -------------------- ----- add here ----- --file related signal eog_op_a: std_logic; signal eog_op_b: std_logic; signal y_op_a: std_logic_vector(15 downto 0); signal y_op_b: std_logic_vector(15 downto 0); signal rd_en_op_a: std_logic; signal rd_en_op_b: std_logic;

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signal datatosave : real; file stimulus_op_a: text open read_mode is "op_a.dat"; file stimulus_op_b: text open read_mode is "op_b.dat"; -------------------- begin -- instantiate the unit under test (uut) uut: combinationnaladder port map ( clk => clk, rst => rst, op_ready => op_ready, op_a => op_a, op_b => op_b, result => result, result_ready => result_ready ); ----- add here ----- write_result_process: process file outfile : text is out "result.dat"; variable outline : line; begin if result_ready = '1' then datatosave <= real(to_integer(signed(result))); wait until clk = '0' and clk'event; write(outline, datatosave, right, 16, 12); writeline(outfile, outline); else wait until clk = '0' and clk'event; end if; end process; read_op_a_process: process variable l: line; variable s: string(1 to 16); begin eog_op_a <= '0'; -- wait for reset to complete wait until rst='1'; wait until rst='0'; while not endfile(stimulus_op_a) loop wait until (clk = '1' and rd_en_op_a = '1'); -- read digital data from input file readline(stimulus_op_a, l); read(l, s); y_op_a <= to_std_logic_vector(s);

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end loop; eog_op_a <= '1'; wait; end process read_op_a_process; read_op_b_process: process variable l: line; variable s: string(1 to 16); begin eog_op_b <= '0'; -- wait for reset to complete wait until rst='1'; wait until rst='0'; while not endfile(stimulus_op_b) loop wait until (clk = '1' and rd_en_op_b = '1'); -- read digital data from input file readline(stimulus_op_b, l); read(l, s); y_op_b <= to_std_logic_vector(s); end loop; eog_op_b <= '1'; wait; end process read_op_b_process; -------------------- -- clock process definitions clk_process :process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- stimulus process stim_proc: process begin -- hold reset state for 100 ns. ----- add here ----- rd_en_op_a <= '0';

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rd_en_op_b <= '0'; rst <= '1'; -------------------- wait for 100 ns; wait for clk_period*100; -- insert stimulus here ----- add here ----- rd_en_op_a <= '1'; rd_en_op_b <= '1'; rst <= '0'; wait for clk_period; wait until clk'event and clk = '1'; while eog_op_a = '0' and eog_op_b = '0' loop --add your stimulation code here end loop; --manage the module latency here --add your stimulation code here -------------------- wait; end process; end;

Figure8.Testbenchtemplate.Thistemplateincludesallthenecessaryprocessesforinput/output.

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Figure9.ISimwindowsafterthesimulation.

Post-Route simulation with ISim

Step 1. Change the behavioral simulation to Post-route, like in Figure 10.

Step 2. Right click on "Simulate Post-Place & Route Model" and select "Process Properties...". change the "simulation Run Time" to 100000 ns. Select "Use Custom Project File" and in the "Custom Project Filename" set the path to the "combinationnalAdder_custom.prj" file provided with this lab. Your configuration should look like Figure 11. Note: this configuration file will replace the architecture of your combinationnalAdder entity by the one generated by the synthesizer. This new architecture includes the timing properties of the routed design. If you made modifications in your VHDL code since you synthesized it, you will have to re-synthesize it again before running the simulation.

Step 3. Double click on "Simulate Post-Place & Route Model". Look at your simulation results and provide a print screen of it in your report (like in step 10 of the behavioral simulation).

Step 4. In your test bench, change the clock period to 2.5 ns and re-run the simulation. Repeat step 10 of the "Creation of a test bench and behavioral simulation with ISim" section.

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Q6: Put the your VHDL code and the content of result.dat in your report. What is happening? Why the results differs from the previous simulations?

Figure10.Post-routesimulationselection.

Figure11.Post-routesimulationparametermodifications.

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Pipelined adder

Another way to implement the adder is to use a pipelined architecture. Basically, pipelining consists of splitting the circuit in multiple smallest circuit working in parallel. This technique is used intensively in signal processing and in all modern processors.

Step 1. Follow the steps 1-5 of the section "Creating a project with Xilinx ISE" to create a project called pipelinedAdder.

Step 2. Follow the steps 6-7 of the section "Creating a project with Xilinx ISE" to create a VHDL file called pipelinedAdder.vhd. Give the same inputs/outputs than the combinationnalAdder entity.

Step 3. A pipelined addition mainly consists of cascading one half adder stage with full adders stages, and by inserting memory elements between the stages, as seen in Figure 12. Implement the missing VHDL code for the pipelined adder of Figure 13 (implements the stages 4 and 5). Note: you can use all the built-in logic operations (NOT, OR, XOR, etc.), but no additions. Provide your VHDL code in your report.

Step 4. Once the VHDL design is implemented, expand the "User Constraints" in the "Processes" tab. Double click on "I/O Pin Planning (PlanAhead) - Pre-Synthesis". The software " PlanAhead " will open, fill the site section for each pin as is Figure 7. Save and close PlanAhead.

Step 5. In the "Processes" tab, double click on "Implement Design". The synthesizing of your design can take 1-2 minutes. If there is no error in your VHDL code, you should see " Process ""Generate Post-Place & Route Static Timing" completed successfully " when the synthesizing is finished.

Step 6. In the IDE console, locate the maximum frequency achievable by your design. Put a screenshot of the console output indicating this value in your report.

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Step 7. Validate your design with a behavioral simulation. Use the same code that was used for the combinationnalAdder test bench (modify the entity and instantiation names). Make sure the files "op_a.dat", "op_b.dat" and "pipelinedAdder_custom.prj" are in your project workspace and don't forget to add "txt_util.vhd".

Step 8. Redo all the steps of the "Post-Route simulation with ISim". Use 2.5 ns for the clock period.

Step 9. In the temporal simulation, zoom enough to make the results visible and provide a print screen in your report. You can also check the test bench results in the "result.dat" file produced by the simulation.

Q7: Do you notice something compared with the combinational architecture? Provide a short explanation in your report. Is there a way to improve the speed of the pipelined architecture? How?

Q8: In your report, provide one advantage and one inconvenient for both the pipelined and combinational implementations of the adder.

Q9: Design a VHDL module that has the same entity as Figure 14. This module has to implement a pipelined architecture to performs D_out = A_in + B_in + C_in. You have to reuse the combinational adder and you have to design a test bench to test it. Report your VHDL code, your test bench and a ISim waveform.

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Q

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Figure12.6-bitspipelinedadderon6stages.

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library ieee; use ieee.std_logic_1164.all; entity pipelinedadder is port ( clk : in std_logic; rst : in std_logic; op_a : in std_logic_vector (5 downto 0); op_b : in std_logic_vector (5 downto 0); op_ready : in std_logic; result : out std_logic_vector (6 downto 0); result_ready : out std_logic); end pipelinedadder; architecture behavioral of pipelinedadder is --stage 1 signal op_a_xor_op_b_stage_1: std_logic_vector(4 downto 0); signal op_a_and_op_b_stage_1: std_logic_vector(5 downto 0); signal op_a_bit_5_stage_1: std_logic; signal op_b_bit_5_stage_1: std_logic; signal result_bit_0_stage_1: std_logic; signal result_ready_stage_1: std_logic; --stage 2 signal op_a_xor_op_b_stage_2: std_logic_vector(3 downto 0); signal op_a_and_op_b_stage_2: std_logic_vector(4 downto 0); signal op_a_bit_5_stage_2: std_logic; signal op_b_bit_5_stage_2: std_logic; signal result_bit_0to1_stage_2: std_logic_vector(1 downto 0); signal result_ready_stage_2: std_logic; --stage 3 signal op_a_xor_op_b_stage_3: std_logic_vector(2 downto 0); signal op_a_and_op_b_stage_3: std_logic_vector(3 downto 0); signal op_a_bit_5_stage_3: std_logic; signal op_b_bit_5_stage_3: std_logic; signal result_bit_0to2_stage_3: std_logic_vector(2 downto 0); signal result_ready_stage_3: std_logic; --stage 4 --add code here --stage 5 --add code here --stage 6 signal result_bit_0to6_stage_6: std_logic_vector(6 downto 0); begin calculation_pipeline_process: process(clk, rst) begin if rst = '1' then --optional result_ready <= '0'; result_ready_stage_1 <= '0'; result_ready_stage_2 <= '0'; result_ready_stage_3 <= '0';

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result_ready_stage_4 <= '0'; result_ready_stage_5 <= '0'; elsif (clk'event and clk = '1') then --pipeline stage 1 op_a_xor_op_b_stage_1 <= op_a(5 downto 1) xor op_b(5 downto 1); op_a_and_op_b_stage_1 <= op_a and op_b; result_bit_0_stage_1 <= op_a(0) xor op_b(0); op_a_bit_5_stage_1 <= op_a(5); op_b_bit_5_stage_1 <= op_b(5); result_ready_stage_1 <= op_ready; --pipeline stage 2 op_a_xor_op_b_stage_2 <= op_a_xor_op_b_stage_1(4 downto 1); op_a_and_op_b_stage_2(4 downto 1) <= op_a_and_op_b_stage_1(5 downto 2); result_bit_0to1_stage_2 <= (op_a_xor_op_b_stage_1(0) xor op_a_and_op_b_stage_1(0)) & result_bit_0_stage_1; op_a_and_op_b_stage_2(0) <= (op_a_xor_op_b_stage_1(0) and op_a_and_op_b_stage_1(0)) or op_a_and_op_b_stage_1(1); op_a_bit_5_stage_2 <= op_a_bit_5_stage_1; op_b_bit_5_stage_2 <= op_b_bit_5_stage_1; result_ready_stage_2 <= result_ready_stage_1; --pipeline stage 3 op_a_xor_op_b_stage_3 <= op_a_xor_op_b_stage_2(3 downto 1); op_a_and_op_b_stage_3(3 downto 1) <= op_a_and_op_b_stage_2(4 downto 2); result_bit_0to2_stage_3 <= (op_a_xor_op_b_stage_2(0) xor op_a_and_op_b_stage_2(0)) & result_bit_0to1_stage_2; op_a_and_op_b_stage_3(0) <= (op_a_xor_op_b_stage_2(0) and op_a_and_op_b_stage_2(0)) or op_a_and_op_b_stage_2(1); op_a_bit_5_stage_3 <= op_a_bit_5_stage_2; op_b_bit_5_stage_3 <= op_b_bit_5_stage_2; result_ready_stage_3 <= result_ready_stage_2; --pipeline stage 4 --add code here --pipeline stage 5 --add code here --pipeline stage 6 result <= (((op_a_and_op_b_stage_5(0) and op_a_xor_op_b_stage_5(0)) or op_a_and_op_b_stage_5(1)) xor op_a_bit_5_stage_5 xor op_b_bit_5_stage_5) & (op_a_xor_op_b_stage_5(0) xor op_a_and_op_b_stage_5(0)) & result_bit_0to4_stage_5; result_ready <= result_ready_stage_5; end if; end process; end behavioral;

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Figure13.Implementationofthe6-bitspipelinedadderon6stages,thestages4-5aremissing

entity complex_adder is port( A_in : in std_logic_vector(4 downto 0); B_in : in std_logic(4 downto 0); C_in : in std_logic(5 downto 0); D_out : out std_logic(6 downto 0); ); end complex_adder;

Figure14.EntitytobeimplementedinQ9.

How to launch Modelsim

Modelsim and ISim are mainly the same software. However, ISim is configured by ISE when the simulation in launched, when Modelsim has to be configured manually on the server. This is a small introduction on Modelsim, showing you how to launch it on the server.

Step 1: In a terminal, log on the server using the same procedure as in labs 1 and 2.

Step 2. Type:

tcsh

source/CMC/scripts/mentor.modelsim.10.3.csh

vsim

Step 3. In the library tab, right click in a blank space and select "New->Library...". In the pop-up window, select "a map to an existing library", and enter the library path: "/CMC/kits/artisan18.3.0/FE/aci/sc/vhdl/tsmc18vhd".

Step 4. Now you are ready for lab 4.

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Report

• Write a report that will include the following parts:

o An introduction

o Your answers to the questions

o All the requested curves and screenshots

o A conclusion

Print the last page of this document and use it as the first page of your report. Make sure to submit your report before the deadline.

GIF-4201 (Micro-électronique)

Lab 3: FPGA and VLSI Design

Nom Matricule

1.

2.

Signature de l’assistant : Date :