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Lab 3: Analog-to-Digital Conversion (ADC)

Fall 2019

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Analog-to-Digital Conversion

• Acquire analog inputs from the potentiometer and observe the result using the debugger

• Using an oscilloscope, measure the time required to complete one conversion by toggling GPIO

• Acquire a sine wave signal from the function generator and investigate aliasing– Generate a square wave signal from

the input sine function and observe output signal frequency on the digital oscilloscope

– Use the “software oscilloscope” to output the acquired signal to the serial port for display on the monitor

Software Oscilloscope Display

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Analog-to-Digital Conversion• Chapter 42 S32K144 Reference

Manual• Two 16-channel, 12-bit Successive

Approximation ADCs– ADC0 and ADC1

• A conversion can be triggered by software or hardware.

• Single (one conversion) or continuous conversion modes.

• Calibration of ADC using reference voltages for higher accuracy.

• Hardware averaging of multiple conversions.

Successive Approximation ADC

• Employs DAC and comparator• N-bit register MSB is set to 1

(DAC output = VREF/2)• If VIN is greater than VDAC, the

MSB of the N-bit register remains at 1. Conversely, if VIN is less than VDAC, the MSB of the register is cleared

• The SAR control logic then moves to the next bit down, forces that bit high, and does another comparison

• Sequence continues all the way down to the LSB at which point conversion is complete

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megahertz (MHz), the ADC sample rate is a fraction of that number due to thesuccessive-approximation algorithm.

SAR ADC ArchitectureAlthough there are many variations for implementing a SAR ADC, the basicarchitecture is quite simple (see Figure 1). The analog input voltage (V ) isheld on a track/hold. To implement the binary search algorithm, the N-bitregister is first set to midscale (that is, 100... .00, where the MSB is set to 1).This forces the DAC output (V ) to be V /2, where V is the referencevoltage provided to the ADC. A comparison is then performed to determine ifV is less than, or greater than, V . If V is greater than V , thecomparator output is a logic high, or 1, and the MSB of the N-bit registerremains at 1. Conversely, if V is less than V , the comparator output is alogic low and the MSB of the register is cleared to logic 0. The SAR control logicthen moves to the next bit down, forces that bit high, and does anothercomparison. The sequence continues all the way down to the LSB. Once this isdone, the conversion is complete and the N-bit digital word is available in theregister.

Figure 1. Simplified N-bit SAR ADC architecture.

Figure 2 shows an example of a 4-bit conversion. The y-axis (and the bold linein the figure) represents the DAC output voltage. In the example, the firstcomparison shows that V < V . Thus, bit 3 is set to 0. The DAC is then set to0100 and the second comparison is performed. As V > V , bit 2 remains at1. The DAC is then set to 0110 , and the third comparison is performed. Bit 1 isset to 0, and the DAC is then set to 0101 for the final comparison. Finally, bit 0

IN

DAC REF REF

IN DAC IN DAC

IN DAC

IN DAC

2 IN DAC

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Understanding SAR ADCs: Their Architecture and Comparison... http://www.maximintegrated.com/en/app-notes/index.mvp/id/1080

2 of 10 8/27/14 9:35 AM

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Analog-to-Digital Conversion

• We will use ADC0 in software controlled single conversion mode

• Three functions required:– Initialize ADC0 single mode conversion: init_ADC0_single– Wait for completed conversion: ADC0_complete– Read ADC0 single mode conversion: read_ADC0_single

• Before configuring the ADC, must set the clock using the Peripheral Clock Control (PCC) registers.

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ANin

GND

GND

5V

5V

6 4 2 0

7 5 3 1

Potentiometer(Turning Knob)

PotJump (Connector)

Interface Board Connections to ADC6

ADC0 channels 1-7 connected toANin[0] – ANin[7]

Jumper connects rotary potentiometer to input channel ANin[0]

• We are using input channel 0 of ADC0, which maps to pin PTA0that is connected to analog input channel ANin[1] on the interface board.

Configure the PCC ADC0 Register

• Section 29.6.19

– Clear the CGC bit to disable the lock– Choose the PCS bitfield to select clock option 1– Set the CGC bit to enable the clock

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Peripheral Clocking

• Clock option 1– SOSCDIV2_CLK (8 MHz – see eecs461.h)

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ADC Configuration Registers9

• Configure several registers:- SC1[0], SC2, SC3, CFG1, CFG2

• Read result from R[0]register

ADC Status and Control Register 1: SC1[0]

• SC1[0], referred to in the manual as SC1A, is used for software triggered ADCs – other SC1 registers used only for hardware triggered ADCs.

– ADCH: selects channel to be used for conversion (reset value 0x1Fdisables ADC for configuration – see Table 41-2, NOT Section 42.4.2.)

– AIEN: enables interrupt when conversion completed (not used).– COCO: conversion completed – set when conversion is completed,

cleared when results register is read

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ADC Configuration Register 1: CFG111

• Selects ADC resolution and clock

- ADICLK: selects input clock source = ALTCLK1(see Table 27-9.)

- MODE: selects ADC resolution, we want 12 bit conversions- ADIV: clock divider (leave set at 1)

• Selects ADC sample time- the time taken to capture an analog signal

- SMPLTS: selects sample time from 2-256 ADC clock cycles.- the value of SMPLTS = sample time -1.- reset value: SMPLTS = 0b1100 yields sample time 13 clock cycles

ADC Configuration Register 2: CFG212

• Selects SW or HW triggered conversion

- ADACT: indicates when a conversion is in progress.- ADTRG: SW or HW trigger – when SW trigger is selected, a

conversion is initiated following a write to SC1[0]- REFSEL: reference voltage – default to external pins VREFH and VREFL

Status and Control Register 2: SC213

• Controls conversion mode, calibration, and averaging

- ADCO: selects single or continuous conversions- CAL: enables calibration (disable)- AVGE: enables hardware averaging (disable)- AVGS: number of ADCs averaged (N/A)

Status and Control Register 3: SC314

• Contains the result of an AD conversion• In single conversion mode, data will be in R[0]

- D: data result (bits 0:11 for a 12-bit conversion).

ADC Data Result Register: R[0]15

S32K144 Register Definitions: ADC16

/** ADC - Register Layout Typedef */typedef struct {

__IO uint32_t SC1[ADC_SC1_COUNT]; /*ADC Status and Control Register 1, array offset: 0x0, array step: 0x4 */

__IO uint32_t CFG1; /* ADC Configuration Register 1, offset: 0x40 */__IO uint32_t CFG2; /* ADC Configuration Register 2, offset: 0x44 */__I uint32_t R[ADC_R_COUNT]; /* ADC Data Result Registers, array offset: 0x48,

array step: 0x4 */...

__IO uint32_t SC2; /* Status and Control Register 2, offset: 0x90 */__IO uint32_t SC3; /* Status and Control Register 3, offset: 0x94 */

...} ADC_Type, *ADC_MemMapPtr;

.../* ADC - Peripheral instance base addresses *//** Peripheral ADC0 base address */#define ADC0_BASE (0x4003B000u)/** Peripheral ADC0 base pointer */#define ADC0 ((ADC_Type *)ADC0_BASE)

.../* CFG2 Bit Fields */#define ADC_CFG2_SMPLTS_MASK 0xFFu#define ADC_CFG2_SMPLTS_SHIFT 0u#define ADC_CFG2_SMPLTS_WIDTH 8u#define ADC_CFG2_SMPLTS(x) /* see S32K144.h */

ADC sampling and conversion timing• Total conversion time consists of the sample time, the

compare time plus additional overhead time, and depends on the ADC clock (8 MHz) and the bus clock (40 MHz).

• When a conversion is started, the ADC connects an internal capacitor to an analog input pin, allowing the capacitor to charge up to the input voltage value.

• The time to load the capacitor is the sample time. After completion of the sampling phase, the compare phase starts and all the bits corresponding to the resolution of the ADC are estimated to provide the conversion result.

• See Section 42.5.4.5 of the S32K144 reference manual.

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Lab 3 Functions

• Three functions to be completed in adc_template.c• init_ADC0_single

– Configure the ADC for SW trigger & specified conversion mode and sample time.

• ADC0_complete– Returns COCO bit from SC1 register.

• Read_ADC0_single– Initiate conversion by writing to ADCH bitfield of SC1 register.– Wait for conversion to complete.– Read result register.

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adc_template.c Code Snippetvoid init_ADC0_single(void) {/* Table 27-9 Peripheral module clocking *//* 29.6.19 PCC ADC0 Register (PCC_ADC0) */PCC->PCCn[PCC_ADC0_INDEX] /* fill in */; /* Disable clock to change PCS */PCC->PCCn[PCC_ADC0_INDEX] /* fill in */; /* Select clock option 1 */PCC->PCCn[PCC_ADC0_INDEX] /* fill in */; /* Enable clock */

/*42.4.2 - ADC Status and Control Register 1 (SC1AA - SC1Z)*/ADC0->SC1[0] /* fill in */; /* Disable Module *//* fill in */; /* Disable interrupts */

/*42.4.3 - ADC Configuration Register 1: CFG1 */

ADC0->CFG1 /* fill in */; /* Alternate clock 1 *//* fill in */; /* 12-bit conversion *//* fill in */; /* Prescaler=1 */

/*42.4.4 - ADC Configuration Register 2: CFG2 */

ADC0->CFG2 /* fill in */; /* set sample time to 13 ADC clks */

/*42.4.7 - Status and Control Register 2: SC2 */ADC0->SC2 /* fill in */; /* SW trigger *//* fill in */; /* use voltage reference pins VREFH & VREEFL */

/*42.4.8 - Status and Control Register 3: SC3 */

ADC0->SC3 /* fill in */; /* Do not start calibration sequence *//* fill in */; /* One conversion performed (single mode) *//* fill in */; /* HW average function disabled *//* fill in */;

}

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Lab 3 Assignment

• Single Conversion Mode Testing – Write a simple C program called lab3.c

that uses the init_ADC0_single and read_ADC0_single functions from adc.c to retrieve the value of an analog input from the potentiometer and store it to a variable called iAnalog.

– Use the debugger and potentiometer to verify that data are being acquired correctly

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Lab 3 Assignment

• Timing– Modify your lab3.c file so that, before the

call to the read_ADC0_single function, one of the LEDs is set to high and is set back to low after the function returns.

– Connect an oscilloscope to the GPO output pin and measure and record:

• the amount of time required for one execution of the function read_ADC0_single

• the amount of time between successive calls to the function read_ADC0_single

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Lab 3 Assignment

• Aliasing– Generate a square wave by toggling the

GPIO with respect to an input signal threshold (a sine wave input will result in a square wave output of the same frequency)

– Increase the input frequency and observe what happens

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Sine Wave to Square Wave

sine wave f0 = 2kHzsoftware loop* fs = 20kHzf0 << fN = fs/2: no aliasing

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1−1.5

−1

−0.5

0

0.5

1

1.5f0 =2000Hz, fs =20000 Hz

time , milliseconds

sin(2πf0t )sin(2πf0kTs)square wave

sine wave f0 = 19kHzsoftware loop* fs = 20kHzf0 > fN è alias fa = 1 kHz

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1−1.5

−1

−0.5

0

0.5

1

1.5f0 =19000Hz, fs =20000 Hz

time , milliseconds

sin(2πf0t )sin(2πf0kTs)square wave

* The loop timing you will measure in Lab 3 should be much faster.

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Lab 3 Assignment

• Oscilloscope Application– Use the provided software and Simulink model– What is the highest-frequency signal you are able to

capture and display without aliasing?• You will see signal phenomena that are NOT

aliasing: Don’t be confused– Read “Sampling, Beats, and the Software Oscilloscope”available on Canvas