Lab 11 Report

ECE 270

Lab Project 11: Basic Memory Circuits

Group members; Jakshay Desai, Nathan Onsare

Introduction

Memory circuits can largely be seperated into two major groups: dyanamic memories that store

data for use in a computer system (such as the RAM in a PC); and static memories that store

information that defines the operating state of a digital system. Dynamic memory circuits for

computer systems have become very specialized, and they will be covered in a later lab. This

exercise will present memory circuits that are used to store information about the operating state

of a digital system.

Procedures

Problem 1.

Created a NAND basic cell in the Xilinx tools using structural VHDL methods. Added a 1ns gate

delay to both NAND gates (for both rising and falling transitions). We then Labeled inputs S and

R and the outputs Q and QN as appropriate. Create a VHDL test bench to simulate the circuit,

driving the inputs as specified below

De-assert both inputs at the start of the simulation. At 100ns, asset S. At 200ns, de-assert S. At

300ns, assert R. At 400ns, de-assert R. At 500ns, assert both inputs. At 600ns, de-assert both

inputs. At 700ns, assert both inputs.

1. An undefined output

2. A set operation

3. A reset operation

4. A ‘0’ being stored in memory

5. A ‘1’ being stored in memory

6. A state where the Q and QN outputs are both driven to the same

value

7. A metastable state

Problem 3.

Modify the test bench for the NAND basic cell by de-asserting S at 600ns and R at 601ns, and

resimulate. Comment on any differences in the output, and more importantly, give a reason for

any differences seen.

Problem 4.

Starting with the NAND basic cell, create a new source file for a D-latch. Be sure the basic cell

NAND gates have a 1ns gate delay. Create and run a VHDL test bench to simulate this circuit,

and be sure to test all possible combinations of inputs to fully document the circuit’s function. At

some point during the simulation, illustrate the property of D-latch transparency (i.e., show the

circuit behavior when gate input is high, and the D input changes from L-H-L or H-L-H), and

also illustrate a metastable state. Mark on a printout of the simulation waveform the following

output behaviors: an undefined output, transparency, storing a ‘1’, storing a ‘0’, and

metastability. Submit the source file and annotated timing diagram.

Problem 5.

Create a behavioral source file for a RET DFF. Name the inputs D and CLK, and the output Q.

Create a VHDL test bench to simulate the flip-flop, driving CLK and D appropriately. What do

you notice about the output Q? Why?

Add an asynchronous reset, and assert the reset signal at the start of the simulation, de-asserting

it after a small amount of time. Resimulate, and demonstrate the proper operation of your flip-

flop.

Modify the simulation, and try to force a metastable state. Can you force a metastable state? Print

and submit your source file, and a single simulation file showing proper flip-flop operation and

your attempt to get it into a metastable state. Have the lab assistance inspect your work.

Result/Analysis

While conducting this experiment, we did not encounter any problems at all. Moreover, all of the

simulations were accurate as proved by the lab instructor but we finished on time to finish the

problem 3. However, all the schematics were good and all the logic equations were noted to be

correct. In addition, from the structural VHDL file from the schematic we outlined all the inputs

and outputs on the schematic.

On the other hand, we checked that all the schematics were properly connected to the inputs of

the gates so that on the simulation we do not get any undecided readings. Hence there were no

red indicators between nodes of the schematic. Lastly, we double checked our output simulations

by checking them using a pencil and paper to check the 1’s and 0’s to make certain that software

were accurate.

Errors and Troubleshooting

As far as this lab is concerned some errors were found while building the schematics and during

simulations. The program was unable to complete the simulation when the schematic wasn’t

saved yet. During the creation of the .bit file we had several troubleshooting errors because of

which we were unable to create a .bit file and enter it into the circuit board.

Conclusion

From this experiment, we can say that our designs are accurate; the signals displayed on the

simulation for problem 3 were verified by the lab instructor and were assumed to be correct. In

addition, we gained a good understanding of what was taught in lecture and we applied it to a

practical real design.

AppendixProblem1

VHDLlibrary IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity problem1 is

Port ( s : in STD_LOGIC;

r : in STD_LOGIC;

q : inout STD_LOGIC;

qn : inout STD_LOGIC);

end problem1;

architecture Behavioral of problem1 is

begin

q <= (s nand qn)after 1ns;

qn <= (r nand q)after 1ns;

end Behavioral;

TESTBENCHLIBRARY ieee;

USE ieee.std_logic_1164.ALL;



--USE ieee.numeric_std.ALL;

ENTITY problem1TB IS

END problem1TB;

ARCHITECTURE behavior OF problem1TB IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT problem1

PORT(

s : IN std_logic;

r : IN std_logic;

q : INOUT std_logic;

qn : INOUT std_logic

);

END COMPONENT;

--Inputs

signal s : std_logic := '0';

signal r : std_logic := '0';

--Outputs

signal q : std_logic;

signal qn : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: problem1 PORT MAP (

s => s,

r => r,

q => q,

qn => qn

);

-- Stimulus process

stim_proc: process

begin

s <= '1';

r <= '1';

wait for 100 ns;

s <= '0';

wait for 100 ns;

s <= '1';

wait for 100 ns;

r <= '0';

wait for 100 ns;

r <= '1';

wait for 100 ns;

s <= '0';

r <= '0';

wait for 100 ns;

s <= '1';

r <= '1';

wait for 100 ns;

s <= '0';

r <= '0';

wait for 100 ns;

end process;

END;

PROBLEM 2VHDL

library IEEE;







--library UNISIM;


entity problem3 is

Port ( R : in STD_LOGIC;

S : in STD_LOGIC;

Q : inout STD_LOGIC;

QN : inout STD_LOGIC);

end problem3;


begin

Q <= (S nand QN)after 1ns;

QN <= (R nand Q)after 1ns;

end Behavioral;

TESTBENCHLIBRARY ieee;

USE ieee.std_logic_1164.ALL;



--USE ieee.numeric_std.ALL;

ENTITY problem1TB IS

END problem1TB;

ARCHITECTURE behavior OF problem1TB IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT problem1

PORT(

s : IN std_logic;

r : IN std_logic;

q : INOUT std_logic;

qn : INOUT std_logic

);

END COMPONENT;

--Inputs

signal s : std_logic := '0';

signal r : std_logic := '0';

--Outputs

signal q : std_logic;

signal qn : std_logic;

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: problem1 PORT MAP (

s => s,

r => r,

q => q,

qn => qn

);

-- Stimulus process

stim_proc: process

begin

s <= '1';

r <= '1';

wait for 100 ns;

s <= '0';

wait for 100 ns;

s <= '1';

wait for 100 ns;

r <= '0';

wait for 100 ns;

r <= '1';

wait for 100 ns;

s <= '0';

r <= '0';

wait for 100 ns;

s <= '1';WAIT FOR 1 NS;r <= '1';

wait for 100 ns;

s <= '0';

r <= '0';

wait for 100 ns;

end process;

END;

SIMULATION

Problem 3VHDLlibrary IEEE;







--library UNISIM;


entity problem4 is

Port ( R : in STD_LOGIC;

S : in STD_LOGIC;



end problem4;


begin

Q <= (S nand QN)after 1ns;

QN <= (R nand Q)after 1ns;

end Behavioral;

DLATCH

library IEEE;







--library UNISIM;


entity problem4_component is

Port ( S : inout STD_LOGIC;

R : inout STD_LOGIC;

D : in STD_LOGIC;

G : in STD_LOGIC;



end problem4_component;

architecture Behavioral of problem4_component is

begin

S <= (D nand G) AFTER 1 NS;

R <= ((not D) Nand G) AFTER 1 NS ;

Q <= (S nand QN)AFTER 1 NS;

QN <= (R nand Q)AFTER 1 NS;

end Behavioral;

TESTBENCHLIBRARY ieee;USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--USE ieee.numeric_std.ALL; ENTITY p4_TB ISEND p4_TB; ARCHITECTURE behavior OF p4_TB IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT problem4_component PORT( S : INOUT std_logic; R : INOUT std_logic; D : IN std_logic; G : IN std_logic; Q : INOUT std_logic; QN : INOUT std_logic ); END COMPONENT;

--Inputs signal S : std_logic; signal R : std_logic; signal D : std_logic := '0'; signal G : std_logic := '0';

--BiDirs signal Q : std_logic;

--Outputs signal QN : std_logic; -- No clocks detected in port list. Replace <clock> below with -- appropriate port name BEGIN

-- Instantiate the Unit Under Test (UUT) uut: problem4_component PORT MAP ( S => S, R => R, D => D, G => G, Q => Q, QN => QN );

-- Stimulus process stim_proc: process begin D <= '1';

wait for 10 ns;

G <='1';

wait for 10 ns;

G <= '0';

wait for 10 ns;

G <='1';

wait for 10 ns;

D <= '0';

G <= '0';

wait for 5 ns;

D <= '0';

G <='1';

wait for 4 ns;

D <= '1';

G <= '1';

wait for 1 ns;

D <= '1';

G <= '0';

wait for 10 ns;

G <='1';

wait for 10 ns;

D <= '0';

wait for 10 ns;

D <='1';

wait for 10 ns;

D <= '0';

wait for 10 ns;

G <='1';

wait for 10 ns;

G <= '0';

wait for 10 ns;

G <='1';

wait for 10 ns;

wait; end process;

END;

SIMULATION

PROBLEM 5VHDLlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity PROBLEM5 is Port ( D : in STD_LOGIC; clk : in STD_LOGIC; rst:in STD_LOgic; Q : OUT STD_LOGIC);end PROBLEM5;

architecture Behavioral of PROBLEM5 is

beginprocess(clk)beginif (clk'event and clk='1')then Q<=D;end if ;end process;end Behavioral;

TESTBENCHLIBRARY ieee;USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--USE ieee.numeric_std.ALL; ENTITY problemtb5 ISEND problemtb5; ARCHITECTURE behavior OF problemtb5 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT PROBLEM5 PORT( D : IN std_logic; clk : IN std_logic; rst : IN std_logic; Q : OUT std_logic ); END COMPONENT;

--Inputs signal D : std_logic := '0'; signal clk : std_logic := '0'; signal rst : std_logic := '0'; signal Q : std_logic := '0';

BEGIN

-- Instantiate the Unit Under Test (UUT) uut: PROBLEM5 PORT MAP ( D => D, clk => clk, rst => rst, Q => Q );

-- Stimulus process stim_proc: process begin

D<='0'; CLK<='0'; WAIT FOR 10 NS; D<='0'; CLK<='1'; WAIT FOR 10 NS; D<='1'; CLK<='0'; WAIT FOR 10 NS; D<='1'; CLK<='1';

wait; end process;

END;

SIMULATION

RESET PARTVHDLlibrary IEEE;use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating-- any Xilinx primitives in this code.--library UNISIM;--use UNISIM.VComponents.all;

entity PROBLEM5 is Port ( D : in STD_LOGIC;

clk : in STD_LOGIC; rst:in STD_LOgic;

ce:in STD_LOgic; Q : OUT STD_LOGIC);end PROBLEM5;

architecture Behavioral of PROBLEM5 is

beginprocess(clk,rst)beginif rst='1' then Q<='0';elsif (clk'event and clk='1')then if ce='1'then Q<=D;end if ;end if;end process;end Behavioral;

TESTBENCHLIBRARY ieee;USE ieee.std_logic_1164.ALL; -- Uncomment the following library declaration if using-- arithmetic functions with Signed or Unsigned values--USE ieee.numeric_std.ALL; ENTITY problemtb5 ISEND problemtb5; ARCHITECTURE behavior OF problemtb5 IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT PROBLEM5 PORT( D : IN std_logic; clk : IN std_logic;

ce:in STD_LOgic; rst : IN std_logic; Q : OUT std_logic ); END COMPONENT;

--Inputs signal D : std_logic := '0'; signal clk : std_logic := '0'; signal rst : std_logic := '0';

signal ce: STD_LOgic:='1';

signal Q : std_logic := '0';

BEGIN

-- Instantiate the Unit Under Test (UUT) uut: PROBLEM5 PORT MAP ( D => D, clk => clk, rst => rst,

ce=>ce, Q => Q );

-- Stimulus process stim_proc: process begin

D<='0'; CLK<='0'; WAIT FOR 10 NS; D<='0'; CLK<='1'; WAIT FOR 10 NS; D<='1'; CLK<='0'; WAIT FOR 10 NS; D<='1'; CLK<='1';

wait; end process;

END;

SIMULATION

Lab 11 Report

Documents

Transcript of Lab 11 Report