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ARM

Introduction &Instruction Set Architecture

Aleksandar MilenkovicE-mail: [email protected]

Web: http://www.ece.uah.edu/~milenka

mailto:[email protected]://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkamailto:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]

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2

Outline

ARM Architecture

ARM Organization and Implementation

ARM Instruction Set

Thumb Instruction Set

Architectural Support for SystemDevelopment

ARM Processor ores

Memory !ierarchy

Architectural Support for Operating Systems

ARM P" ores

#mbedded ARM Applications

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3

ARM History

ARM – Acorn RISC Machine (1983 – 1985) Acorn Computers Limited, Camrid!e, "n!#and

ARM – Ad$anced RISC Machine 199% ARM Limited, 199%

ARM has een #icensed to man& semiconductormanu'acturers

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4

ARM’s visible registers

ser #e$e# 15 *Rs, *C,

C*SR (currentpro!ramstatus

re!ister) Remainin!

re!isters areused 'or s&stem+#e$e#

pro!rammin!and 'or hand#in!eceptions

r13_und

r14_undr14_irq

r13_irq

SS!_und

r14_abtr14_"#c

u"er m$de%iq

m$de"#c

m$deab$rtm$de

irqm$de

unde%inedm$de

u"able in u"er m$de

"&"tem m$de" $nl&

r13_abtr13_"#c

r'_%iq

r(_%iq

r1)_%iq

r11_%iq

SS!_irqSS!_abtSS!_"#cSS!_%iq*S!

r14_%iq

r13_%iq

r1+_%iq

r)r1

r+

r3

r4

r,

r

r

r'

r(r1)

r11

r1+

r13

r14

r1, *0

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ARM memory organiation

Linear arra& o' &tes numered'rom % to 3 – 1

7ata items

&tes (8 its)

ha#'+ords (14 its) – a#a&s

a#i!ned to +&te oundaries(start at an e$en &te address)

ords (3 its) – a#a&sa#i!ned to +&te oundaries(start at a &te address hich

is mu#tip#e o' )

hal%-w$rd4

w$rd1

)1+3

4,

'(1)11

b&te)

b&te

1+13141,

111'1(

+)+1+++3

b&te1b&te+

hal%-w$rd14

b&te3

b&te

addre""

bit 31 bit )

hal%-w$rd1+

w$rd'

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ARM instruction set

Load+store architecture operands are in *Rs

#oadstore – on#& instructions that operate ith memor&

Instructions

7ata *rocessin! – use and chan!e on#& re!ister $a#ues 7ata 2rans'er – cop& memor& $a#ues into re!isters

(#oad) or cop& re!ister $a#ues into memor& (store)

Contro# 6#oo ranch

o ranch+and+#in: –sa$e return address to resume the ori!ina# se;uence

o trappin! into s&stem code – super$isor ca##s

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ARM instruction set !cont’d"

2hree+address data processin! instructions

Conditiona# eecution o' e$er& instruction

*oer'u# #oadstore mu#tip#e re!ister instructions

Ai#it& to per'orm a !enera# shi't operation and a

!enera# AL operation in a sin!#e instruction thateecutes in a sin!#e c#oc: c&c#e

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I#O system

I< is memor& mapped interna# re!isters o' periphera#s (dis: contro##ers,

netor: inter'aces, etc) are addressa#e #ocationsithin the ARM=s memor& map and ma& e read andritten usin! the #oad+store instructions

*eriphera#s ma& use either the norma# interrupt(IR>) or 'ast interrupt (6I>) input norma##& most interrupt sources share the IR> input,

hi#e ?ust one or to time+critica# sources are

connected to the 6I> input Some s&stems ma& inc#ude eterna# 7MA hardare

to hand#e hi!h+andidth I< tra@c

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ARM e$ce%tions

ARM supports a ran!e o' interrupts, traps, and super$isor ca##s –a## are !rouped under the !enera# headin! o' eceptions

and#in! eceptions

current state is sa$ed & cop&in! the *C into r1Bec and C*SRinto S*SRBec (ec stands 'or eception t&pe)

processor operatin! mode is chan!ed to the appropriateeception mode

*C is 'orced to a $a#ue eteen %%14 and 1C14, the particu#ar$a#ue dependin! on the t&pe o' eception

instruction at the #ocation *C is 'orced to (the $ector address)usua##& contains a ranch to the eception hand#er the

eception hand#er i## use r13Bec, hich is norma##& initia#iDedto point to a dedicated stac: in memor&, to sa$e some userre!isters

returnE restore the user re!isters and then restore *C andC*SR atomica##&

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ARM crossdevelo%ment tool'it

So'tare de$e#opment too#s de$e#oped &

ARM Limited

pu#ic domain too#s(ARM ac: end 'or!cc C compi#er)

Cross+de$e#opment too#s run on diFerent

architecture 'rom one

'or hich the&produce code

assemblerC compiler

C source asm source

.aof

C libraries

linker

.axf

ARMsd

debug

ARMulator development

system model

board

objectlibraries

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Outline

ARM Architecture

ARM Assembly $anguage Programming

ARM Organization and Implementation

ARM Instruction Set

Architectural Support for !igh%level $anguages Thumb Instruction Set

Architectural Support for System Development

ARM Processor ores

Memory !ierarchy

Architectural Support for Operating Systems

ARM P" ores


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ARM Instruction Set

7ata *rocessin! Instructions 7ata 2rans'er Instructions

Contro# 0o Instructions

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(ata Processing Instructions

C#asses o' data processin! instructions Arithmetic operations

Git+ise #o!ica# operations

Re!ister+mo$ement operations

Comparison operations

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(ata Processing Instructions !cont’d"

ADD r0, r1, r2 r0 := r1 + r2

ADC r0, r1, r2 r0 := r1 + r2 + C

SUB r0, r1, r2 r0 := r1 - r2

SBC r0, r1, r2 r0 := r1 - r2 + C - 1

RSB r0, r1, r2 r0 := r2 – r1

RSC r0, r1, r2 r0 := r2 – r1 + C - 1

7rithmetic 8perati$n" 9it-wi"e $;ical 8perati$n"

AND r0, r1, r2 r0 := r1 and r2

ORR r0, r1, r2 r0 := r1 or r2

EOR r0, r1, r2 r0 := r1 xor r2

BIC r0, r1, r2 r0 := r1 and (not) r2

!e;i"ter

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(ata Processing Instructions !cont’d"

Immediate operandsEimmediate (%+H55) n, % n 1

Shi'ted re!ister operands the second operand is su?ect to a shi't operation

e'ore it is comined ith the Jrst operand

ADD r', r2, r1, S ' r' := r2 + * x r1

ADD r, r, r', S r2 r := r + 2r2 x r'

ADD r', r', ' r' := r' + '

AND r*, r, .. r* := r/:0, .or #x

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ARM shift o%erations

LSL – Lo!ica# Shi't Le't LSR – Lo!ica# Shi't Ri!ht

ASR – Arithmetic Shi'tRi!ht

R

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Setting the condition codes

An& 7*I can set the condition codes (-, ., /, and C) 'or a## 7*Is ecept the comparison operationsa speciJc re;uest must e made

at the assem#& #an!ua!e #e$e# this re;uest is indicated& addin! an S to the opcode

"amp#e (r3+r E r1+r% r3+r)

Arithmetic operations set a## the 0a!s (-, ., C, and /)

Lo!ica# and mo$e operations set - and . preser$e / and either preser$e C hen there is no shi't

operation, or set C accordin! to shi't operation ('a## oFit)

ADDS r2, r2, r0

ADC r', r', r1

$arr3 o4t to C

555 add 6nto 67 8ord

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Multi%lies

"amp#e (Mu#tip#&, Mu#tip#&+Accumu#ate)

-ote

#east si!niJcant 3+its are p#aced in the resu#t re!ister,the rest are i!nored immediate second operand is not supported resu#t re!ister must not e the same

as the Jrst source re!ister

i' S it is set the / is preser$ed andthe C is rendered meanin!#ess

"amp#e (r% r% 35) ADD r0, r0, r0, S 2 r09 = r0 x

RSB r', r', r1 r099 = x r09

MU r, r', r2 r := /r' x r2;'1:0<

MA r, r', r2, r1 r := /r' x r2 + r1 ;'1:0<

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(ata transfer instructions

Sin!#e re!ister #oad and store instructions trans'er o' a data item (&te, ha#'+ord, ord)

eteen ARM re!isters and memor&

Mu#tip#e re!ister #oad and store instructions

ena#e trans'er o' #ar!e ;uantities o' data used 'or procedure entr& and eit, to sa$erestore

or:space re!isters, to cop& #oc:s o' data aroundmemor&

Sin!#e re!ister sap instructions a##o echan!e eteen a re!ister and memor&

in one instruction

used to imp#ement semaphores to ensure mutua#ec#usion on accesses to shared data in mu#tis

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(ata )ransfer Instructions !cont’d"

DR r0, /r1 r0 := #'2/r1

S%R r0, /r1 #'2/r1 := r0$te: r1 keep" a w$rd addre"" + S9" are )0

DR r0, /r1, r0 := #'2/r1 +

!e;i"ter-indirect addre""in;

9a"e>$%%"et addre""in;

$%%"et $% up t$ 4?b&te"0

DR r0, /r1, > r0 := #'2/r1 +

r1 := r1 +

7ut$-indein; addre""in;

DR r0, /r1, r0 := #'2/r1

r1 := r1 +

$"t-indeed addre""in;

DRB r0, /r1 r0 := #*

/r1$te: n$ re"tricti$n" %$r r1

Single register load and store

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(ata )ransfer Instructions !cont’d"

CO!?: ADR r1, %ABE1 r1 @o6nt" to %ABE1

ADR r2, %ABE2 r2 @o6nt" to %ABE2

OO!: DR r0, /r1

S%R r0, /r2

ADD r1, r1,

ADD r2, r2, 555

%ABE1: 555

%ABE2:555CO!?: ADR r1, %ABE1 r1 @o6nt" to %ABE1

ADR r2, %ABE2 r2 @o6nt" to %ABE2

OO!: DR r0, /r1,

S%R r0, /r2,

555

%ABE1: 555

%ABE2:555

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(ata )ransfer Instructions

G#oc: cop& $ie

data is to e stored above or belo& the the addresshe#d in the ase re!ister

address incrementin! ordecrementin! e!insbefore or after storin!the Jrst $a#ue

DMIA r1, r0, r2, r r0 := #'2/r1

r2 := #'2/r1 +

r := #'2/r1 + *$te: an& "ub"et $r all0 $% the re;i"ter" ma& be

tran"%erred with a "in;le in"tructi$n$te: the $rder $% re;i"ter" within the li"t i"

in"i;ni%icant

$te: includin; r1, in the li"t will cau"e a chan;e

in the c$ntr$l %l$w

Multiple register data transfers

Stac: or!aniDations

6A – 'u## ascendin!

"A – empt& ascendin!

67 – 'u## descendin!

"7 – empt& descendin!

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Multi%le register transfer addressing

modes

r,

r1

r(A

r)r(

STMIA r9!, {r0,r1,r5}

1)))1

1))c1

1)1'1

r1r,r(

STMDA r9!, {r0,r1,r5}

r)

r(A 1)))1

1))c1

1)1'1

r,r(

STMDB r9!, {r0,r1,r5}

r1

r)r(A 1)))1

1))c1

1)1'1

r,

r1

r)

r(A

r(

STMIB r9!, {r0,r1,r5}

1)))1

1))c1

1)1'1

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)he ma%%ing bet*een the stac' and

bloc' co%y vie*s

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Control flo* instructions

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Conditional e$ecution

Conditiona# eecution to a$oid ranch instructionsused to s:ip a sma## numer o' non+ranchinstructions

"amp#eCM! r0,

BE& B?!ASS 6. (r0>=) ADD r1, r1, r0 r1:=r1+r0-r2

SUB r1, r1, r2

B?!ASS: 555

CM! r0,

ADDNE r1, r1, r0

SUBNE r1, r1, r2

555

With c$nditi$nal eecuti$n

$te: add + Bletter c$nditi$n a%ter the 3-letter $pc$de

6. ((a==) ($==d)) #++

CM! r0, r1

CM!E& r2, r'

ADDE& r, r, 1

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+ranch and lin' instructions

Granch to suroutine (r1 ser$es as a #in: re!ister)

-ested suroutines

B SUBR ran$ to SUBR

55 r#t4rn #r#

SUBR: 55 SUBR #ntr3 @o6nt

MO @$, r1 r#t4rn

B SUB1

55

SUB1: "a# 8or and F6n r#76"t#r

S%MGD r1'>, r0-r2,r1B SUB2

55

DMGD r1'>, r0-r2,@$

SUB2: 55

MO @$, r1 $o@3 r1 6nto r1

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Su%ervisor calls

Super$isor is a pro!ram hich operates at apri$i#e!ed #e$e# – it can do thin!s that a user+#e$e#pro!ram cannot do direct#& "amp#eE send tet to the disp#a&

ARM ISA inc#udes SNI (So'tNare Interrupt) o4t@4t r0/:0

SHI SHIHr6t#C

r#t4rn .ro a 4"#r @ro7ra a$ to on6tor

SHI SHIEx6t

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,um% tables

Ca## one o' a set o' suroutines dependin! on a$a#ue computed & the pro!ram

B J%AB

555

J%AB: CM! r0, 0

BE& SUB0

CM! r0, 1

BE& SUB1

CM! r0, 2

BE& SUB2

$te: "l$w when the li"t i" l$n;=

and all "ubr$utine" are equall&

%requent

B J%AB

555

J%AB: ADR r1, SUB%AB

CM! r0, SUBMAK o#rr4nL

DRS @$, /r1, r0, S 2

B ERROR

SUB%AB:DCD SUB0

DCD SUB1

DCD SUB2

555

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Hello ARM -orld.

AREA #FFoH, CODE, READON? d#$Far# $od# ar#aSHIHr6t#C E&U 0 o4t@4t $ara$t#r 6n r0

SHIEx6t E&U 11 .6n6" @ro7ra

EN%R? $od# #ntr3 @o6nt

S%AR%: ADR r1, %EK% r1 ;- #FFo ARM HorFd>

OO!: DRB r0, /r1, 1 7#t t# n#xt 3t#CM! r0, 0 $#$ .or t#xt #nd

SHINE SHIHr6t#C 6. not #nd o. "tr6n7, @r6nt

BNE OO!

SHI SHIEx6t #nd o. #x#$4t6on

%EK% = #FFo ARM HorFd>, 0a, 0d, 0

END

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ARM

Organiation and Im%lementation

Aleksandar MilenkovicE-mail: [email protected]

Web: http://www.ece.uah.edu/~milenka

mailto:[email protected]://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkahttp://www.ece.uah.edu/~milenkamailto:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]:[email protected]

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Outline

ARM Architecture ARM Organization and Implementation

ARM Instruction Set

Architectural Support for !igh%level $anguages

Thumb Instruction Set Architectural Support for System Development

ARM Processor ores

Memory !ierarchy

Architectural Support for Operating Systems ARM P" ores


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ARM organiation

Re!ister J#e – read ports, 1 rite port 1 read, 1 rite port reser$ed'or r15 (pc)

Garre# shi'ter – shi't or rotate

one operand 'or an& numero' its AL – per'orms the arithmetic

and #o!ic 'unctions re;uired Memor& address re!ister

incrementer Memor& data re!isters Instruction decoder and

associated contro# #o!ic

multipl&

data $ut re;i"ter

in"tructi$n

dec$de

Cc$ntr$l

incrementer

re;i"ter bank

addre"" re;i"ter

barrel"hi%ter

7D31:)

FD31:)

data in re;i"ter

7G

c$ntr$l

*

*

7G bu"

7 bu"

9 bu"

re;i"ter

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)hreestage %i%eline

6etch the instruction is 'etched 'rom memor& and p#aced inthe instruction pipe#ine

7ecode

the instruction is decoded and the datapath contro#si!na#s prepared 'or the net c&c#e in this sta!e theinstruction ons the decode #o!ic ut not thedatapath

"ecute

the instruction ons the datapath the re!ister an:is read, an operand shi'ted, the AL re!ister!enerated and ritten ac: into a destination re!ister

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ARM singlecycle instruction %i%eline

%etch dec$de e@ecute

time

1



2

3

in"tructi$n

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ARM singlecycle instruction %i%eline

add r0,r1,#5

sub r2,r3,r6

cmp r2,#3

fetch

time

decode

fetch

execute add

decode

fetch

execute sub

decode execute cmp

1 2 3

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ARM multicycle instruction %i%eline

%etch 7FF dec$de eecute

time

1

%etch S6! dec$de calc. addr .

%etch 7FF dec$de eecute

2

3

data %er

%etch 7FF dec$de eecute4

5 %etch 7FF dec$de eecutein"tructi$n

Fec$de l$;ic i" alwa&" ;eneratin;the c$ntr$l "i;nal" %$r the datapath

t$ u"e in the net c&cle

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ARM multicycle /(MIA !load

multi%le" instruction

fetch decodeex ld r2ldmia r0,{r2,r3}

sub r2,r3,r6

cmp r2,#3

ex ld r3

fetch

time

decode ex sub

fetch decodeex cmp

Decode stage occupiedsince ldmia must continue to

remember decoded instruction

sub fetched at normal time but

not decoded until D!"# is finishing

"nstruction dela$ed

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Control stalls0 due to branches

Granches o'ten introduce sta##s (ranch pena#t&) Sta## time ma& depend on hether ranch is ta:en

Ma& ha$e to s;uash instructionsthat a#read& started eecutin!

7on=t :no hat to 'etch unti# condition ise$a#uated

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ARM %i%elined branch

time

fetch decodeex bnebne foo

sub

r2,r3,r6fetch decode

foo add

r0,r,r2

ex bne

fetch decodeex add

ex bne

Decision not made until the third cloc% c$cle

&'o c$cles of 'or% thro'na'a$ if bne ta%es place

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Pi%eline0 ho* it *or's

A## instructions occup& the datapath'or one or more ad?acent c&c#es

6or each c&c#e that an instruction occupies thedatapath,it occupies the decode #o!ic inthe immediate#& precedin! c&c#e

7urin! the Jst datapath c&c#e each instructionissuesa 'etch 'or the net instruction ut one

Granch instruction 0ush and reJ## the instructionpipe#ine

ARM1)(MI

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ARM1)(MI

2stage %i%elineI-cache

rot/sgn ex

+4

byte repl.

ALU

I decode

register read

D-cache

fetch

instructiondecode

execute

buffer/ data

write-back

forwardingpaths

immediatefields

nextpc

regshift

load/storeaddress

LDR pc

SUBS pc

post-index

pre-index

LDM/STM

register write

r15

pc + 8

pc + 4

+4

mux

shift

mul

B, BLMOV pc

6etch 7ecode

instruction is decoded re!ister operands read

(3 read ports)

"ecute an operand is shi'ted and

the AL resu#t!enerated, or

address is computed

GuFerdata data memor& is

accessed (#oad, store) Nrite+ac:

rite to re!ister J#e

ARM1)(MI

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ARM1)(MI

(ata 3or*ardingI-cache

rot/sgn ex

+4

byte repl.

ALU

I decode

register read

D-cache

fetch

instructiondecode

execute

buffer/ data

write-back

forwardingpaths

immediatefields

nextpc

regshift

load/storeaddress

LDR pc

SUBS pc

post-index

pre-index

LDM/STM

register write

r15

pc + 8

pc + 4

+4

mux

shift

mul

B, BLMOV pc

ADD r', r2, r1, S '

ADD r, r, r', S r2

r' := r2 + * x r1

r := r + 2r2 x r'

ADD r', r2, r1, S '

ADD r*, rP, r10ADD r, r, r', S r2

r' := r2 + * x r1

r* := rP + r10r := r + 2r2 x r'

D r', /r2

ADD r1, r2, r'

r' := #/r2

r1 := r2 + r'

Data Forwarding

Stall?

ARM1)(MI

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ARM1)(MI

PC generationI-cache

rot/sgn ex

+4

byte repl.

ALU

I decode

register read

D-cache

fetch

instructiondecode

execute

buffer/ data

write-back

forwardingpaths

immediatefields

nextpc

regshift

load/storeaddress

LDR pc

SUBS pc

post-index

pre-index

LDM/STM

register write

r15

pc + 8

pc + 4

+4

mux

shift

mul

B, BLMOV pc

3+sta!e pipe#ine *C eha$iorE

operands are read ineecution sta!er15 *C 8

5+sta!e pipe#ine

operands are read in decodesta!e and r15 *C O

incompatii#ities eteen 3+sta!e and 5+sta!eimp#ementations H

unaccepta#e to a$oid this 5+sta!epipe#ine ARMs emu#ate theeha$ior o' the o#der 3+sta!e desi!ns

( t i i t ti

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(ata %rocessing instruction

data%ath activity !4$"

addre"" re;i"ter

increment

re;i"ter"!d

!n

*

!m

a" in".

a" in"tructi$n

mult

data $ut data in i. pipe

(a) register – register operations

addre"" re;i"ter

increment

re;i"ter"!d

!n

*

a" in".

a" in"tructi$n

mult


D:)

(b) register – immediate operations

Re!+Re!Rd Rn op

Rmr15 AR

AR AR

Re!+ImmRd Rn op

Immr15 AR

AR AR

S)R ! t i t " d t th ti it

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S)R !store register" data%ath activity

!4$56 4$7"

addre"" re;i"ter

increment

re;i"ter"!n

*

l"l H)

I 7 / 7 > 9 / 7 - 9

mult


D11:)

addre"" re;i"ter

increment

re;i"ter"

!n

!d

"hi%ter

I 7 > 9 / 7 - 9

mult

*

b&teJ data in i. pipe

(a) 1 st cycle – compute address (b) 2nd cycle – store data & auto-index

Computeaddress ("1)AR Rn op

7ispr15 AR

Store data(")AR *CmemPARQ

RdE&HI'

autoindein!HRn Rn +

)h fi t t ! f th " l f

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)he first t*o !of three" cycles of a

branch instruction

addre"" re;i"ter

increment

re;i"ter"*

l"l H+

I 7 > 9

mult


D+3:)

addre"" re;i"ter

increment

re;i"ter"!14

*

"hi%ter

I 7

mult


(a) 1 st cycle – compute branch target (b) 2nd cycle – save return address

Tird c!cle" do a s#all

correction to te value

stored in te link register in

order tat it points todirectl! at te instruction

wic follows te $ranc?

Compute tar!etaddressAR *C 7isp,#s#

Sa$e return address

(i' re;uired)r1 *CAR AR

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ARM Im%lementation

7atapath R2L (Re!ister 2rans'er Le$e#)

Contro# unit 6SM (6inite State Machine)

7 %hase non o erla%%ing cloc'

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7%hase nonoverla%%ing cloc'

scheme Most ARMs do not operate on ed!e+sensiti$e

re!isters

Instead the desi!n is ased around+phase non+o$er#appin! c#oc:s hich are!enerated interna##& 'rom a sin!#e c#oc: si!na#

7ata mo$ement is contro##ed & passin! the dataa#ternati$e#& throu!h #atcheshich are open durin! phase 1 or #atches durin!phase

1 cl$ck c&cle

pha"e 1

pha"e +

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ARM data%ath timing

Re!ister read Re!ister read uses – d&namic, prechar!ed durin! phase 7urin! phase 1 se#ected re!isters dischar!e the read uses

hich ecome $a#id ear#& in phase 1

Shi't operation second operand passes throu!h arre# shi'ter

AL operation AL has input #atches hich are open in phase 1,

a##oin! the operands to e!in cominin! in ALas soon as the& are $a#id, ut the& c#ose at the end o' phase 1

so that the phase prechar!e does not !et throu!h to the AL AL processes the operands durin! the phase , producin! the

$a#id output toards the end o' the phase the resu#t is #atched in the destination re!ister

at the end o' phase

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ARM data%ath timing !cont’d"

read bu" #alid

"hi%t $ut #alid

7G $ut

"hi%t time

7G time

re;i"ter write time

re;i"ter readtime

7G $perand"

latched

pha"e 1

pha"e +

prechar;ein#alidate"bu"e"

Mini#u# Datapat Dela! %

&egister read ti#e '

Sifter Dela! ' A() Dela! '

&egister write set*up ti#e ' +ase 2 to pase 1 non*overlap ti#e

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)he original ARM5 ri%%lecarry adder

Carr& #o!icE use CM

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ARM7 8bit carry loo'ahead scheme

Carr& enerate ()Carr& *ropa!ate (*)

CoutP3Q CinP%Q*

se A

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)he ARM7 A/9 logic for one result bit

AL 'unctions data operations (add, su, )

address computations 'or memor& accesses

ranch tar!et computations

it+ise #o!ica#operations

7G

bu"

43+1),

9

bu"

7bu"

carr&

l$;ic

% ":

K

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ARM7 A/9 function codes

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)he ARM: carryselect adder scheme

Compute sumso' $arious Je#dso' the ord'or carr&+in o'Dero and carr&+

in o' one 6ina# resu#t is

se#ected &usin! the

correct carr&+in$a#ue to contro#a mu#tip#eor

"umD31:1"umD1,:'"umD:4"umD3:)

" ">1

a=bD31:+'a=bD3:)

> >= >1

c

>= >1

mu

mu

mu

'orst case(O)log*+&ord &idth,- gates

long

-oteE Ge care'u#T 6an+out on some o' these!ates is hi!h so direct comparison ithpre$ious schemes is not app#ica#e

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)he ARM: A/9 organiation

-ot eas& to mer!e the arithmetic and #o!ic'unctions Ha separate #o!ic unit runs in para##e# ith the adder,

and mu#tip#eor se#ects the output

2

*

l$;ic/arithmetic

* in%uncti$n

in#ert 7 in#ert 9

re"ult

re"ul t mu@

l$;ic %uncti$n"

7 $perand latch 9 $perand latch

L8! ;ate" L8! ;ate"

adder

Mer$ detect

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ARM1 carry arbitration encoding

Carr& aritration adder

ai i Ci $i, i

% % % %, %

1 1 1 1, 1

1 % u 1, %

% 1 u 1, %

ai i ai+1 i+1 Ci $i, i

% % + + % %, %

1 1 + + 1 1, 1

%(1

)

1(%

)

% % % %, %

%(1)

1(%)

1 1 1 1, 1

%(1)

1(%)

%(1)

1(%)

u 1, %

iii

iiibawba#

⋅=

+=

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)he crossbar s*itch barrel shifter

Shi'ter de#a& is critica# since it contriutes direct#&to the datapath c&c#e time

Cross+ar sitch matri (3 3)

*rincip#e 'or matri

inD)

inD1

inD+

inD3

$utD) $utD1 $utD+ $utD3

n$ "hi%tri;ht 1ri;ht +ri;ht 3

le%t 1

le%t +

le%t 3


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!cont’d" *rechar!ed #o!ic is used H

each sitch is a sin!#e -M

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Multi%lier design

A## ARMs apart 'orm the Jrst protot&pe ha$e inc#udedsupport 'or inte!er mu#tip#ication o#der ARM cores inc#ude #o+cost mu#tip#ication hardare

that supports on#& the 3+it resu#t mu#tip#& andmu#tip#&+accumu#ate

recent ARM cores ha$e hi!h+per'ormance mu#tip#icationhardare and support 4+it resu#t mu#tip#& andmu#tip#&+accumu#ate

Lo cost imp#ementation se the datapath iterati$e#&, emp#o&in! the arre# shi'ter

and AL to !enerate +it product in each c#oc: c&c#e use ear#& termination to stop the iterations hen there

are no more ones in the mu#tip#& re!ister

)he 7bit multi%lication algorithm

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)he 7bit multi%lication algorithm6

;th cycle Contro# settin!s 'or the -th c&c#e o' the

mu#tip#ication

se eistin! shi'ter and AL additiona# hardare dedicated to+its+per+c&c#e shi't re!ister 'or the

mu#tip#ier and a 'e !ates 'or the Gooth=s a#!orithm

contro# #o!ic(o$erhead is a 'e per cent on the area o' ARM core)

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High s%eed multi%lication

Nhere mu#tip#ication per'ormance is $er&important,more hardare resources must e dedicated in some emedded s&stems the ARM core is used to

per'orm rea#+time di!ita# si!na# processin! (7S*) –

7S* pro!rams are t&pica##& mu#tip#ication intensi$e se intermediate resu#ts hich inc#ude

partia# sums and partia# carries Carr&+sa$e adders are used 'or this

2hese to inar& resu#ts are added to!ether at theend o' mu#tip#ication 2he main AL is used 'or this

Carry%ro%agate !a" and carrysave

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Carry%ro%agate !a" and carrysave

!b" adder structures Carr& propa!ate adder ta:es to con$entiona# (irredundant)

inar& numers as inputs and produces a inar& sum Carr& sa$e adder ta:es one inar& and one redundant (partia#

sum and partia# carr&) input and produces a sum in redundantinar& representation (sum and carr&)

> 7 9 *in

*$ut Sa0 >

7 9 *in

*$ut S>

7 9 *in

*$ut S>

7 9 *in

*$ut S

> 7 9 *in

*$ut Sb0 >

7 9 *in

*$ut S>

7 9 *in

*$ut S>

7 9 *in

*$ut S

ARM highs%eed multi%lier

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organiation CSA has #a&ers o' adders each hand#in!

mu#tip#ier itsH mu#tip#& 8+its per c#oc: c&c#e

*artia# sum and carr& are c#eared at the e!innin!or initia#iDed to accumu#ate a $a#ue

Mu#tip#ier is shi'ted ri!ht 8+itsper c&c#e in the URs= re!ister

Carr& sum and carr&are rotated ri!ht 8 its per c&c#e

*er'ormanceE up to c#oc: c&c#es(ear#& termination is possi#e)

Comp#eit&E 14% its in shi't re!isters,18 its o' carr&+sa$e adder #o!ic(up to 1%V o' simp#er cores)


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ARM high s%eed multi%lier

organiation

!" NN ' bit"/c&cle

carr&-"a#e adder"

partial "um

partial carr&

initialiMa ti$n % $r

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ARM7 register cell circuit

7 bu"9 bu"

7:G bu"

writeread

9read 7

ARM register ban' floor%lan

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ARM register ban' floor%lan

7 bu" read dec$der"

9 bu" read dec$der"

write dec$der"

re;i"ter cell"*

dd

""

7Gbu"

*bu"

*

bu"

7Gbu"

7 bu"

9 bu"

ARM core data%ath buses

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ARM core data%ath buses

addre"" re;i"ter

incrementer

re;i"ter bank

multiplier

7G

"hi%ter

data in

in"tructi$n pipe

data $ut

7 9

W

in"tructi$n

Fin

"hi%t $ut

*

7d

inc

ARM control logic structure

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ARM control logic structure

dec$de7

c&clec$unt

multipl&

c$ntr$l

l$ad/"t$remultiple

addre""c$ntr$l

re;i"ter c$ntr$l

7Gc$ntr$l

"hi%ter c$ntr$l

in"tructi$n

c$pr$ce""$r

l18_arm

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