L01: Intro, Combinational LogicL21: Virtual Memory II ......Miss Penalty (latency) 33x Miss Penalty...
Transcript of L01: Intro, Combinational LogicL21: Virtual Memory II ......Miss Penalty (latency) 33x Miss Penalty...
3/2/17
1
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
VirtualMemoryIICSE351Winter2017
https://xkcd.com/1495/
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
Administrivia
v Lab4dueFriday,howisitgoing?v HW3graded,posted.
v Planforrestofquarter:§ HW4outtoday,dueMon,Mar6.§ Lab5outFridayMar3,dueMonMar13(cut-offMar15).§ Final:Wed,Mar15th,8:30-10:20,here.
• Materialforthewholequarter.Moredetailsnextweek.
2
3/2/17
2
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
IndirectioninVirtualMemory
3
v Eachprocessgetsitsownprivatevirtualaddressspacev Solves:dealingwithsmallphysicalmemory,memory
management,protection,sharing.
Physical memory
Virtual memory
Virtual memory
Process 1
Process n
mapping
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
VMandtheMemoryHierarchyv Thinkof virtualmemory asarrayofN = 2n contiguousbytesv Pages ofvirtualmemoryareusuallystoredinphysical
memory,butsometimesspilltodisk§ Pagesareanotherunitofalignedmemory(sizeisP = 2p bytes)§ Eachvirtualpagecanbestoredinany physicalpage(nofragmentation!)
4
VP0VP1
VP2n-p-1
Virtualmemory
Unallocated
Unallocated
0
2n-1
PP2m-p-1
PhysicalmemoryEmpty
Empty
PP0PP1
Empty
2m-1
0
Virtualpages(V
P's)
Disk
Physicalpages(PP's)
“SwapSpace”
3/2/17
3
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
MemoryHierarchy:Core2Duo
5
DiskMainMemory
L2unifiedcache
L1I-cache
L1D-cache
CPU Reg
2B/cycle8B/cycle16B/cycle 1B/30cyclesThroughput:Latency: 100cycles14cycles3cycles millions
~4MB
32KB
~8GB ~500GB
Notdrawntoscale
MissPenalty(latency)
33x
MissPenalty(latency)10,000x
SRAMStaticRandomAccessMemory
DRAMDynamicRandomAccessMemory
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
VirtualMemory(VM)
v Overviewandmotivationv VMasatoolforcachingv Addresstranslationv VMasatoolformemorymanagementv VMasatoolformemoryprotection
6
3/2/17
4
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
AddressTranslation
7
0:1:
M-1:
Mainmemory
MMU
2:3:4:5:6:7:
Physicaladdress(PA)
Data(int/float)
8: ...
CPU
Virtualaddress(VA)
CPUChip
0x40x4100
MemoryManagementUnit
Howdoweperformthevirtual→ physicaladdresstranslation?
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
AddressTranslation:PageTables
v CPU-generatedaddresscanbesplitinto:
§ RequestisVirtualAddress(VA),wantPhysicalAddress(PA)§ NotethatPhysicalOffset=VirtualOffset(page-aligned)
v Uselookuptablethatwecallthepagetable (PT)§ ReplaceVirtualPageNumber(VPN)forPhysicalPageNumber(PPN)togeneratePhysicalAddress
§ IndexPTusingVPN:pagetableentry(PTE)storesthePPNplusmanagementbits(e.g.Valid,Dirty,accessrights)
§ Hasanentryforevery virtualpage– why?
VirtualPageNumber PageOffset𝑛-bitaddress:
8
3/2/17
5
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
v Pagetablesstoredinphysicalmemory§ Toobigtofitelsewhere– managedbyMMU&OS
v Howmanypagetablesinthesystem?§ Oneperprocess
PageTableDiagram
9
PageTable(DRAM)
null
null
01
0
01101
Valid PPN/DiskAddrPTE0:0
PTE7:7
PTE1:1PTE2:2PTE3:3PTE4:4PTE5:5PTE6:6
......
Virtualmemory(disk)
VP6
VP3
Virtualpage#
Physicalmemory(DRAM)
PP0
PP3
PP2
PP1
VP1
VP2
VP7
VP4
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
CPU
PageTableAddressTranslation
10
Virtualpagenumber(VPN) Virtualpageoffset(VPO)
Physicalpagenumber(PPN) Physicalpageoffset(PPO)
Virtualaddress(VA)
Physicaladdress(PA)
Valid PPN
Pagetablebaseregister
(PTBR)
PagetablePagetableaddressforprocess
Validbit=0:pagenotinmemory
(pagefault)
Inmostcases,theMMUcanperformthistranslation
withoutsoftwareassistance
3/2/17
6
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
PageHit
v Pagehit: VMreferenceisinphysicalmemory
11
PageTable(DRAM)
null
null
01
0
01101
Valid PPN/DiskAddrPTE0
PTE7......
Virtualaddress
Example: Pagesize=4KiB
0x00740bVirtualAddr:
VPN: PPN:
PhysicalAddr:
Physicalmemory(DRAM)
PP0
PP3
VP1VP2VP7VP4
Virtualmemory(disk)
VP6
VP3
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
PageFault
v Pagefault: VMreferenceisNOT inphysicalmemory
12
PageTable(DRAM)
null
null
01
0
01101
Valid PPN/DiskAddrPTE0
PTE7......
Physicalmemory(DRAM)
PP0
PP3
VP1VP2VP7VP4
Virtualmemory(disk)
VP6
VP3
Virtualaddress
Example: Pagesize=4KiBProvideavirtualaddressrequest(inhex)thatresultsin thisparticularpagefault:
VirtualAddr:
3/2/17
7
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
v Userwritestomemorylocationv Thatportion(page)ofuser’smemory
iscurrentlyondisk
v Pagefaulthandlermustloadpageintophysicalmemoryv Returnstofaultinginstruction:mov isexecutedagain!
§ Successfulonsecondtry
int a[1000];int main (){
a[500] = 13;}
80483b7: c7 05 10 9d 04 08 0d movl $0xd,0x8049d10
Usercode OSKernelcode
exception:pagefaultCreatepageandloadintomemoryreturns
movl
PageFaultException
handle_page_fault:
13
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
HandlingaPageFaultv Pagemisscausespagefault(anexception)
14
PageTable(DRAM)
null
null
01
0
01101
Valid PPN/DiskAddrPTE0
PTE7......
Physicalmemory(DRAM)
PP0
PP3
VP1VP2VP7VP4
Virtualmemory(disk)
VP6
VP3
Virtualaddress
3/2/17
8
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
HandlingaPageFaultv Pagemisscausespagefault(anexception)v Pagefaulthandlerselectsavictim tobeevicted(hereVP4)
15
PageTable(DRAM)
null
null
01
0
01101
Valid PPN/DiskAddrPTE0
PTE7......
Physicalmemory(DRAM)
PP0
PP3
VP1VP2VP7VP4
Virtualmemory(disk)
VP6
VP3
Virtualaddress
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
HandlingaPageFaultv Pagemisscausespagefault(anexception)v Pagefaulthandlerselectsavictim tobeevicted(hereVP4)
16
PageTable(DRAM)
null
null
01
0
01110
Valid PPN/DiskAddrPTE0
PTE7......
Physicalmemory(DRAM)
PP0
PP3
VP1VP2VP7VP3
Virtualmemory(disk)
VP4VP6
Virtualaddress
3/2/17
9
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
HandlingaPageFaultv Pagemisscausespagefault(anexception)v Pagefaulthandlerselectsavictim tobeevicted(hereVP4)v Offendinginstructionisrestarted:pagehit!
17
PageTable(DRAM)
null
null
01
0
01110
Valid PPN/DiskAddrPTE0
PTE7......
Physicalmemory(DRAM)
PP0
PP3
VP1VP2VP7VP3
Virtualmemory(disk)
VP4VP6
Virtualaddress
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
PeerInstructionQuestion
v Howmanybitswidearethefollowingfields?§ 16KiBpages§ 48-bitvirtualaddresses§ 16GiB physicalmemory
18
34 24(A)32 18(B)30 20(C)34 20(D)
VPN PPN
3/2/17
10
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
Summary
v Virtualmemoryprovides:§ Abilitytouselimitedmemory(RAM)acrossmultipleprocesses
§ Illusionofcontiguousvirtualaddressspaceforeachprocess§ Protectionandsharingamongstprocesses
v Indirectionviaaddressmappingbypagetables§ Partofmemorymanagementunitandstoredinmemory§ Usevirtualpagenumberasindexintolookuptablethatholdsphysicalpagenumber,diskaddress,orNULL(unallocatedpage)
§ Onpagefault,throwexceptionandmovepagefromswapspace(disk)tomainmemory
19
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
VirtualMemory(VM)
v Overviewandmotivationv VMasatoolforcachingv Addresstranslationv VMasatoolformemorymanagementv VMasatoolformemoryprotection
20
3/2/17
11
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
Review:Terminology
v Contextswitch§ SwitchbetweenprocessesonthesameCPU
v Pagein§ Movepagesofvirtualmemoryfromdisktophysicalmemory
v Pageout§ Movepagesofvirtualmemoryfromphysicalmemorytodisk
v Thrashing§ Totalworkingsetsizeofprocessesislargerthanphysicalmemoryandcausesexcessivepaginginandoutinsteadofdoingusefulcomputation
21
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
VMforManagingMultipleProcessesv Keyabstraction:eachprocesshasitsownvirtualaddressspace
§ Itcanviewmemoryasasimplelineararray
v Withvirtualmemory,thissimplelinearvirtualaddressspaceneednotbecontiguousinphysicalmemory§ ProcessneedstostoredatainanotherVP?Justmapittoany PP!
22
VirtualAddress
SpaceforProcess1:
PhysicalAddressSpace(DRAM)
0
N-1(e.g.,read-onlylibrarycode)
VirtualAddress
SpaceforProcess2:
VP1VP2...
0
N-1
VP1VP2...
PP2
PP6
PP8
...
0
M-1
Addresstranslation
3/2/17
12
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
SimplifyingLinkingandLoadingv Linking
§ Eachprogramhassimilarvirtualaddressspace
§ Code,Data,andHeapalwaysstartatthesameaddresses
v Loading§ execve allocatesvirtualpages
for.text and.data sections&createsPTEsmarkedasinvalid
§ The.text and.data sectionsarecopied,pagebypage,ondemandbythevirtualmemorysystem
23
Kernelvirtualmemory
Memory-mappedregionforsharedlibraries
Run-timeheap(createdbymalloc)
Userstack(createdatruntime)
Unused0
%rsp(stackpointer)
Memoryinvisibletousercode
brk
0x400000
Read/writesegment(.data,.bss)
Read-onlysegment(.init,.text,.rodata)
Loadedfromtheexecutablefile
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
VMforProtectionandSharingv ThemappingofVPstoPPsprovidesasimplemechanismto
protectmemoryandtosharememorybetweenprocesses§ Sharing: mapvirtualpagesinseparateaddressspacestothesame
physicalpage(here:PP6)§ Protection: processcan’taccessphysicalpagestowhichnoneofits
virtualpagesaremapped(here:Process2can’taccessPP2)
24
VirtualAddress
SpaceforProcess1:
PhysicalAddressSpace(DRAM)
0
N-1(e.g.,read-onlylibrarycode)
VirtualAddress
SpaceforProcess2:
VP1VP2...
0
N-1
VP1VP2...
PP2
PP6
PP8
...
0
M-1
Addresstranslation
3/2/17
13
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
MemoryProtectionWithinProcess
v VMimplementsread/write/executepermissions§ Extendpagetableentrieswithpermissionbits§ MMUchecksthesepermissionbitsoneverymemoryaccess
• Ifviolated,raisesexceptionandOSsendsSIGSEGVsignaltoprocess(segmentationfault)
25
•••
PhysicalAddressSpace
PP2
PP4
PP6
PP8PP9
PP11
Processi: PPNWRITE EXECPP6No NoPP4No YesPP2Yes No
READYesYesYes
VP0:VP1:VP2:
YesYesYes
Valid
Processj: WRITE EXECPP9Yes NoPP6No NoPP11Yes No
READYesYesYes
VP0:VP1:VP2:
YesYesYes
Valid PPN
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
AddressTranslation:PageHit
26
1) ProcessorsendsvirtualaddresstoMMU(memorymanagementunit)
2-3)MMUfetchesPTEfrompagetableincache/memory(UsesPTBRtofindbeginningofpagetableforcurrentprocess)
4) MMUsendsphysicaladdress tocache/memoryrequestingdata
5) Cache/memorysendsdatatoprocessor
MMU Cache/MemoryPA
Data
CPU VA
CPUChip PTEA
PTE1
2
3
4
5
VA=VirtualAddress PTEA=PageTableEntryAddress PTE=PageTableEntryPA=PhysicalAddress Data=ContentsofmemorystoredatVAoriginallyrequestedbyCPU
3/2/17
14
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
AddressTranslation:PageFault
27
1) ProcessorsendsvirtualaddresstoMMU2-3) MMUfetchesPTEfrompagetableincache/memory4) Validbitiszero,soMMUtriggerspagefaultexception5) Handleridentifiesvictim(and,ifdirty,pagesitouttodisk)6) HandlerpagesinnewpageandupdatesPTEinmemory7) Handlerreturnstooriginalprocess,restartingfaultinginstruction
MMU Cache/Memory
CPU VA
CPUChip PTEA
PTE1
2
3
4
5
Disk
Pagefaulthandler
Victimpage
Newpage
Exception
6
7
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
Hmm…TranslationSoundsSlow
v TheMMUaccessesmemorytwice:oncetogetthePTEfortranslation,andthenagainfortheactualmemoryrequest§ ThePTEsmay becachedinL1likeanyothermemoryword
• Buttheymaybeevictedbyotherdatareferences
• AndahitintheL1cachestillrequires1-3cycles
v Whatcanwedotomakethisfaster?§ Solution:addanothercache!🎉
28
3/2/17
15
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
SpeedingupTranslationwithaTLB
v TranslationLookasideBuffer (TLB):§ SmallhardwarecacheinMMU§ Mapsvirtualpagenumberstophysicalpagenumbers§ Containscompletepagetableentries forsmallnumberofpages• ModernIntelprocessorshave128or256entriesinTLB
§ Muchfasterthanapagetablelookupincache/memory
29
TLB
PTEVPN →
PTEVPN →
PTEVPN →
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
TLBHit
v ATLBhiteliminatesamemoryaccess!
30
MMU Cache/Memory
PA
Data
CPU VA
CPU Chip
PTE
1
2
4
5
TLB
VPN 3
TLBPTEVPN →
PTEVPN →
PTEVPN →
3/2/17
16
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
TLBMiss
v ATLBmissincursanadditionalmemoryaccess(thePTE)§ Fortunately,TLBmissesarerare
31
MMU Cache/MemoryPA
Data
CPU VA
CPU Chip
PTE
1
2
5
6
TLB
VPN
4
PTEA3
TLBPTEVPN →
PTEVPN →
PTEVPN →
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
FetchingDataonaMemoryRead
1) CheckTLB§ Input:VPN,Output:PPN§ TLBHit: Fetchtranslation,returnPPN§ TLBMiss: Checkpagetable(inmemory)
• PageTableHit: LoadpagetableentryintoTLB• PageFault: Fetchpagefromdisktomemory,updatecorrespondingpagetableentry,thenloadentryintoTLB
2) Checkcache§ Input:physicaladdress,Output:data§ CacheHit: Returndatavaluetoprocessor§ CacheMiss: Fetchdatavaluefrommemory,storeitincache,returnittoprocessor
32
3/2/17
17
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
AddressTranslationVirtualAddress
TLBLookup
PageTable“Walk”
UpdateTLB
PageFault(OSloadspage)
ProtectionCheck
PhysicalAddress
TLBMiss TLBHit
PagenotinMem
AccessDenied
AccessPermitted
ProtectionFault
SIGSEGV
PageinMem
CheckcacheFindinDisk FindinMem
33
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
SummaryofAddressTranslationSymbols
v BasicParameters§ N = 2) Numberofaddressesinvirtualaddressspace§ M = 2+ Numberofaddressesinphysicaladdressspace§ P = 2, Pagesize(bytes)
v Componentsofthevirtualaddress(VA)§ VPO Virtualpageoffset§ VPN Virtualpagenumber§ TLBI TLBindex§ TLBT TLBtag
v Componentsofthephysicaladdress(PA)§ PPO Physicalpageoffset(sameasVPO)§ PPN Physicalpagenumber
34
3/2/17
18
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
SimpleMemorySystemExample(small)
v Addressing§ 14-bitvirtualaddresses§ 12-bitphysicaladdress§ Pagesize=64bytes
13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPOVPNVirtualPageNumber VirtualPageOffset
11 10 9 8 7 6 5 4 3 2 1 0
PPOPPNPhysicalPageNumber PhysicalPageOffset
35
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
SimpleMemorySystem:PageTable
v Onlyshowingfirst16entries(outof_____)§ Note:showing2hexdigitsforPPNeventhoughonly6bits
36
VPN PPN Valid0 28 11 – 02 33 13 02 14 – 05 16 16 – 07 – 0
VPN PPN Valid8 13 19 17 1A 09 1B – 0C – 0D 2D 1E – 0F 0D 1
3/2/17
19
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
SimpleMemorySystem:TLB
v 16entriestotalv 4-waysetassociative
37
13 12 11 10 9 8 7 6 5 4 3 2 1 0
virtualpageoffsetvirtualpagenumber
TLBindexTLBtag
0–021340A10D030–0730–030–060–080–0220–0A0–040–0212D031102070–0010D090–030
ValidPPNTagValidPPNTagValidPPNTagValidPPNTagSet
WhydoestheTLBignorethepageoffset?
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
SimpleMemorySystem:Cache
v Direct-mappedwithK =4B,C/K =16v Physicallyaddressed
38
11 10 9 8 7 6 5 4 3 2 1 0
physicalpageoffsetphysicalpagenumber
cacheoffsetcacheindexcachetag
Note: ItisjustcoincidencethatthePPNisthesamewidth
asthecacheTag
Index Tag Valid B0 B1 B2 B30 19 1 99 11 23 111 15 0 – – – –2 1B 1 00 02 04 083 36 0 – – – –4 32 1 43 6D 8F 095 0D 1 36 72 F0 1D6 31 0 – – – –7 16 1 11 C2 DF 03
Index Tag Valid B0 B1 B2 B38 24 1 3A 00 51 899 2D 0 – – – –A 2D 1 93 15 DA 3BB 0B 0 – – – –C 12 0 – – – –D 16 1 04 96 34 15E 13 1 83 77 1B D3F 14 0 – – – –
3/2/17
20
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
CurrentStateofMemorySystem
39
Cache:
TLB:Pagetable(partial):
Index Tag V B0 B1 B2 B30 19 1 99 11 23 111 15 0 – – – –2 1B 1 00 02 04 083 36 0 – – – –4 32 1 43 6D 8F 095 0D 1 36 72 F0 1D6 31 0 – – – –7 16 1 11 C2 DF 03
Index Tag V B0 B1 B2 B38 24 1 3A 00 51 899 2D 0 – – – –A 2D 1 93 15 DA 3BB 0B 0 – – – –C 12 0 – – – –D 16 1 04 96 34 15E 13 1 83 77 1B D3F 14 0 – – – –
Set Tag PPN V Tag PPN V Tag PPN V Tag PPN V0 03 – 0 09 0D 1 00 – 0 07 02 11 03 2D 1 02 – 0 04 – 0 0A – 02 02 – 0 08 – 0 06 – 0 03 – 03 07 – 0 03 0D 1 0A 34 1 02 – 0
VPN PPN V0 28 11 – 02 33 13 02 14 – 05 16 16 – 07 – 0
VPN PPN V8 13 19 17 1A 09 1B – 0C – 0D 2D 1E – 0F 0D 1
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
MemoryRequestExample#1
v VirtualAddress:0x03D4
v PhysicalAddress:
TLBITLBT
013
012
011
010
19
18
17
16
05
14
03
12
01
00
VPOVPN
11 10 9 8 7 6 5 4 3 2 1 0
PPOPPN
COCICT
VPN______ TLBT_____ TLBI_____ TLBHit?___ PageFault?___ PPN _____
CT______ CI_____ CO_____ CacheHit?___ Data(byte)_______
Note: ItisjustcoincidencethatthePPNisthesamewidth
asthecacheTag
40
3/2/17
21
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
MemoryRequestExample#2
v VirtualAddress:0x038F
v PhysicalAddress:
TLBITLBT
013
012
011
010
19
18
17
06
05
04
13
12
11
10
VPOVPN
11 10 9 8 7 6 5 4 3 2 1 0
PPOPPN
COCICT
VPN______ TLBT_____ TLBI_____ TLBHit?___ PageFault?___ PPN _____
CT______ CI_____ CO_____ CacheHit?___ Data(byte)_______
Note: ItisjustcoincidencethatthePPNisthesamewidth
asthecacheTag
41
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
MemoryRequestExample#3
v VirtualAddress:0x0020
v PhysicalAddress:
TLBITLBT
013
012
011
010
09
08
07
06
15
04
03
02
01
00
VPOVPN
11 10 9 8 7 6 5 4 3 2 1 0
PPOPPN
COCICT
VPN______ TLBT_____ TLBI_____ TLBHit?___ PageFault?___ PPN _____
CT______ CI_____ CO_____ CacheHit?___ Data(byte)_______
Note: ItisjustcoincidencethatthePPNisthesamewidth
asthecacheTag
42
3/2/17
22
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
MemoryRequestExample#4
v VirtualAddress:0x036B
v PhysicalAddress:
TLBITLBT
013
012
011
010
19
18
07
16
15
04
13
02
11
10
VPOVPN
11 10 9 8 7 6 5 4 3 2 1 0
PPOPPN
COCICT
VPN______ TLBT_____ TLBI_____ TLBHit?___ PageFault?___ PPN _____
CT______ CI_____ CO_____ CacheHit?___ Data(byte)_______
Note: ItisjustcoincidencethatthePPNisthesamewidth
asthecacheTag
43
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
VirtualMemorySummary
v Programmer’sviewofvirtualmemory§ Eachprocesshasitsownprivatelinearaddressspace§ Cannotbecorruptedbyotherprocesses
v Systemviewofvirtualmemory§ Usesmemoryefficientlybycachingvirtualmemorypages
• Efficientonlybecauseoflocality
§ Simplifiesmemorymanagementandsharing§ Simplifiesprotectionbyprovidingpermissionschecking
44
3/2/17
23
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
MemorySystemSummaryv MemoryCaches(L1/L2/L3)
§ Purelyaspeed-uptechnique§ Behaviorinvisibletoapplicationprogrammerand(mostly)OS§ Implementedtotallyinhardware
v VirtualMemory§ SupportsmanyOS-relatedfunctions
• Processcreation,taskswitching,protection§ OperatingSystem(software)
• Allocates/sharesphysicalmemoryamongprocesses• Maintainshigh-leveltablestrackingmemorytype,source,sharing• Handlesexceptions,fillsinhardware-definedmappingtables
§ Hardware• Translatesvirtualaddressesviamappingtables,enforcingpermissions• Acceleratesmappingviatranslationcache(TLB)
45
CSE369, Autumn 2016L01: Intro, Combinational Logic CSE351, Winter 2017L21: Virtual Memory II
MemorySystem– Whocontrolswhat?
v MemoryCaches(L1/L2/L3)§ Controlledbyhardware§ Programmercannotcontrolit§ Programmercan writecodetotakeadvantageofit
v VirtualMemory§ ControlledbyOSandhardware§ Programmercannotcontrolmappingtophysicalmemory§ Programmercancontrolsharingandsomeprotection
• viaOSfunctions(notinCSE351)
46