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Reconfigurable Computing Systems

L. LiuDepartment of Computer Science, ETH Zürich

Fall semester, 2012

Reconfigurable Computing Systems (252-2210-00L)Fall 2012

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Reconfigurable Computing Systems (252-2210-00L)

252-2210-00L (4 credits) Part of the master elective courses in Computer Science

Department Lecturers Dr. Ling Liu

Assistant Lars Widmer

http://www.nativesystems.inf.ethz.ch/Main/WebHomeLecturesReconfigurableSystems

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Reconfigurable Computing Systems (252-2210-00L)

Agenda Introduction, Computer arithmetic Verilog DSP introduction FIR, IIR filters General purpose soft-core processor I/O controllers On-chip interconnect Case studies Advanced topics

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Reconfigurable Computing Systems (252-2210-00L)

Textbooks

Scott Hauck and André DeHon, Reconfigurable computing the theory and practice of FPGA-based computation

Steven W. Smith, Digital signal processing : a practical guide for engineers and scientists

Uwe Meyer-Baese, Digital signal processing with Field programmable gate arrays

Niklaus Wirth, Compiler construction

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Reconfigurable Computing Systems (252-2210-00L)

Time Lectures: Wednesday 13:15 – 15:00 Exercises: Friday 13:15 – 14:00

• Exercise assignments will be published on the course web site• Exercises that involve FPGA boards will be finished by groups or

individuals ML510 board

• Exercises are mandatory and will be counted as 50% of your final grade of this course

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Reconfigurable Computing Systems (252-2210-00L)

Evaluation: written exam (50%)

• 90 minutes

Exercise (50%)

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Reconfigurable Computing SystemsFall 2012

Introduction

http://www.nativesystems.inf.ethz.ch/WebHomeLecturesReconfigurableSystems#Contents

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Topics

What is reconfigurable computing? FPGA-based reconfigurable computing Introduction to FPGA

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Example: color conversion

Convert a RGB color video stream into a grayscale video streamY (luminance) = 0.299 * R + 0.587 * G + 0.114 * B

Two implementation approaches General purpose single core RISC processor:

• Performance: 5 cycles• Programmability: flexible

Application-specific integrated circuit (ASIC):• Performance: 3 cycles• Programmability: fixed

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Different Computation Systems

Performance

Programmability

0 10

10 General purpose processor

ASIC

Reconfigurable computer

slowflexible

fastinflexible

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Reconfigurable Computing

Definition: (from John Wawrzynek)computing via a post-fabrication and spatially programmed connection of processing elements

Reconfigurable device examples FPGA - Field programmable gate array

• Medium granularity

CPLD - Complex programmable logic device• Big granularity

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FPGAs: Field Programmable Gate Arrays

Definition FPGAs are pre-fabricated silicon devices that can be electrically programmed to become almost any kind of digital circuit or system.

Compare to ASIC Configuration: takes less than a second instead of months Cost: can be 100,000 times cheaper Area: 20 to 35 times more area Performance: 3 to 4 times slower Power: consumes roughly 10 times as much dynamic power

However, the high costs in ASIC and the need for a proportionally higher return on investment drive most digital design starts toward FPGA implementation

Source: “FPGA Architecture Survey and Challenges” by Ian Kuon, Russell Tessier and Jonathan Rose

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FPGA Usage Models

Fast prototyping Emulating and verifying big circuits SoC (System-on-a-chip)

Audio, video systems Computational biology

Source: http://www.gallery.ethz.ch/inf/view_album.php?set_albumName=Studieninformationstage2012

Source: http://www.gallery.ethz.ch/inf/view_album.php?set_albumName=Studieninformationstage2012

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Xilinx FPGA Technologies

First FPGA devices: Xilinx XC2000 family

developed in 1982.

Basic concept: Programmable logic units Programmable interconnect Programmable I/O

I/O block logic blockinterconnect

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Xilinx Virtex-II FPGA Architecture

Source: FDSP2

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Virtex-5 Configurable Logic Block (CLB)

Used to realize logic functions

Each CLB is connected to a switch matrix

Each CLB contains a pair of slices. Every slice contains: 4 LUTs (look-up tables) 4 registers Wide-function multiplexer Carry logic

Source: FDSP2

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Logic Cell Functionality within a Slice

Source: FDSP2

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Logic Cell Functionality within a Slice

The basic logic cell consists of: A logic resource – a LUT A flip-flop A number of multiplexers A circuit for performing

fast addition

Source: FDSP2

The combination of LUTs, flip-flops (FFs), and special functions such as carry chains and dedicated multiplexers, together with the ways by which these elements are connected, has been termed ExpressFabric technology.

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LUT (look-up table)

A computation can be represented as a Boolean equation.

A Boolean equation can be represented as a truth table. Truth tables are the computational heart of the FPGA. A LUT is a hardware element that can easily implement

a truth table.

Source: RC

Source: RC

A 3-LUT schematic The 3-LUT symbol and truth table for a logic XOR

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Adder Implementation on Xilinx Virtex FPGA Slice

Source: FDSP2

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Memory Organization

Virtex-5 FPGA has a large number of 36kB block RAMS.

Block RAMs are placed in columns and can be cascaded to create deeper and wider RAM blocks

Source: FDSP2

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Virtex-5 DSP Processing Resource

Dedicated DSP processing block called DSP48E. The Virtex-5 can have up to 640 DSP48E slices. DSP48E slices support following functions: Multiply MAC three-input add barrel shifting bit-wise logic functions

Source: FDSP2

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DSP48E Schematic

Source: Xilinx Inc. 2007c

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Implement a SoC on an FPGA

Design system-level architecture. Create a circuit architecture using HDL language, for

example, Verilog, and the commercial synthesizer. Make use of the heterogeneous components of a FPGA device

to achieve better performance, size and power efficiency.• DSPs• BRAMs• LUTs