1

1

2

2

3

3

4

4

5

5

D D

C C

B B

A A

CONFIDENTIAL & PROPRIETARY

REVISIONDESCRIPTIONDATE

Table of Contents

PAGE 01: Revision History

REVISION HISTORY

KSZ8041NL Eval Board Revision 1.0

1.01/4/07 Initial Release

PAGE 02: KSZ8041NL Board -- Block DiagramPAGE 03: KSZ8041NL Device

4/27/07 Added 100pF capacitor (C53) on REXT (pin 10) of KSZ8041NL. 1.1

Revision History 1.1

KSZ8041NL Eval Board

1 3Friday, April 27, 2007

Title

Size Document Number Rev

Date: Sheet of

1

1

2

2

3

3

4

4

5

5

D D

C C

B B

A A

KSZ8041NL EVAL BOARD - BLOCK DIAGRAM

CONFIDENTIAL & PROPRIETARY

MII / RMIISignals

3.3VLDO

KSZ8041NL

10Base-T / 100Base-TXIntegrated Magnetic RJ-45 Jack

Port StatusLEDIndicators

RESET ConfigurationHeaders

MII

/ RM

II Po

rt C

onne

ctor

25 MHz XTAL(MII mode)

5V DCINPUT

50 MHz REF_CLK from MAC(RMII mode)

TX / RX pairs

KSZ8041NL Board -- Block Diagram 1.1

KSZ8041NL Eval Board

2 3Friday, April 27, 2007

Title

Size Document Number Rev

Date: Sheet of

1

1

2

2

3

3

4

4

5

5

D D

C C

B B

A A

CONFIDENTIAL & PROPRIETARY

STEWARDHI1206N101R-00Power_ON

Reset

MII / RMII Port

PushButtonReset

9

CRS_DV

REF_CLK

Output

Input

18

TXD[1]

23

Output

24

Input

TX_EN

TXD[0]

KSZ8893MQLMAC RMII Signals

RXD[1]

Type

Input

Name

RX_ER

CRSDV

Input

20

15

RXD[0]

RXD[0]

RXD[1] TXD[1]

Type

Input

REFCLK

Output

Output

TX_ER

Output

Input

TXD[0]

Input

25

Name

16

Pin #

Input

Output

Output

TX_EN

Input

KSZ8041NLPHY RMII SignalsStrapping Options (Refer to Datasheet for descriptions)

PHYAD0

ISO

CONFIG0

CONFIG2

CONFIG1

PHYAD1

SPEED

DUPLEX

NWAYEN

PHYAD2

RMII Mode (option)The RMII signal connections between KSZ8041NLPHY and external MAC are shown in the table tothe right.

For RMII mode, 1. Remove crystal circuit (Y1, C16, C17) and TXCtermination (R6).

2. Populate R14 with 0 Ohm and R19 with 33 Ohmto connect 50MHz Reference Clock (provided byMAC side via J2 pin 12) to U1 pin 9 (XI input).

3. Select RMII mode by setting strapping pinsCONFIG[2:0] to '001'.

4. Connect J2 (RMII Port) to board with RMII MAC(e.g. Micrel KSZ8893MQL Eval Board).

1. KSZ8041NL has a Paddle Ground on bottom side of chip. Refer to datasheet for mechanical dimensions.

3. Place components (Y1, C16, C17, C53, R14, R15) and (R10, R11, R12, R13, C13, C15) close to respective pins of U1.

2. KSZ8041NL provides the 1.8VPLL supply for VDDPLL_1.8 (pin 2). Decouple 1.8VPLL power rail as shown.

Notes:+5V DCPower Input

Route both traces of each differential pairas identical to each other as possible at 6milwidth/6mil parallel spacing, and at least 18mils away from all other signals.

[01]

ACT

LED Mode

LINK

LED1 SPEED

[00]

LINK/ACTLED0

RJ-45Magnetic Jack

Place SIGNAL_GND return of C14close to SIGNAL_GND at 5V inputpower to board.

C53 is an additional component to the PCB.

Rework C53 in parallel with R15 (as shown) atlocation R15 of PCB.

KSZ8041NL Device 1.1

KSZ8041NL Eval Board

3 3Friday, April 27, 2007

Title

Size Document Number Rev

Date: Sheet of

TXEN_NL

RXD3_NL

RXD1_NL

TXD2_NL

LED0_NL

TXD1_NL

RXD2_NL

RXER_NL

RXD0_NL

RXD1_NL

RXD3_NL

RXDV_NL

LED0_NL

RXD2_NL

COL_NL

CRS_NL

LED1_NL

CRS_NL

RXDV_NL

RST#_NL

INTRP_NL

RXC_NL

MDIO_NL

RXER_NL

RXD0_NL

COL_NL

LED1_NL

TXC_NL

TXD3_NL

TXD0_NL

TX+_NL

TX-_NL

RX+_NL

TX-_NL

TX+_NL

RX-_NL

RX+_NL

XO_NL

XI_NL

CHASSIS_GND_NL

TX-_NLRX+_NL

SIGNAL_GND_NL

LED1_NL

LED0_NL

MDC_NL

RX-_NL

RX-_NL

TX+_NL

1.8VPLL_NL

3.3V_NL3.3V_NL3.3A_NL 5V_NL

3.3V_NL

3.3V_NL

3.3V_NL

3.3A_NL

3.3V_NL

3.3V_NL

3.3A_NL

FB1

FBEAD

12

R2

10K

+

C910uF

R20 33

+

C247uF

C12

0.1uF

J2

Male MII Connector123456789

1011121314151617181920

2122232425262728293031323334353637383940

VCCMDIOMDCRXD3RXD2RXD1RXD0RX_DVRX_CLKRX_ERTX_ERTX_CLKTX_ENTXD0TXD1TXD2TXD3COLCRSVCC

VCCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNCNC

VCC

R3

4.7K

+

C322uF

R17 33

C100.1uF

R16 33

C110.1uF

R7 33

LED1

LEDx2

1 2

3 4

R19

NC

C50.1uF

C17

22pFY1

25MHz

J4 JUMPER R25 4.7K

R10 49.9

J10 JUMPER

C16

22pF

R13 49.9

U2

MIC5216-3.3BM5

1

3

2

4

5 VIN

EN

GND

BYP

OUT

TP2

C150.1uF

R9 33

R31 1K

J3 JUMPER

TP3

+

C147uF

R11 49.9C14

1000pF / 2kV

R8 33

R33 1K

R15

6.49K

TP1

R14 NC

R23 1K

J8 JUMPER

R12 49.9

R6 33

J6 JUMPER

J7 JUMPER

J11 JUMPER

1

757575 75

2345678

1000pF

J1TDK TLA-6T718

910

1

2

4

3

6

5

7

8

SHIE

LDSH

IELD

TD+

TD-

RD+

CT

CT

RD-

NC

CHS_GND

R21 33

C40.1uF

R30 4.7K

R28 4.7K

R22 220

C130.1uF

C53

100pF

S1

SW PUSHBUTTON

1 23 4

R29 4.7K

R1 100K

R32 1K

J12 JUMPER

C70.1uF

J5 JUMPER R26 4.7K

J9 JUMPER

U1KSZ8041NL

12345678

9 10 11 12 13 14 15 16

1718192021222324

2526272829303132

GNDVDDPLL_1.8VDDA_3.3RX-RX+TX-TX+XO

XI REX

TM

DIO

MD

CR

XD3

RXD

2R

XD1

RXD

0

VDDIO_3.3RXDV

RXCRXERINTRP

TXCTXENTXD0

TXD

1TX

D2

TXD

3C

OL

CR

SLE

D0

LED

1R

ST#

+ C810uF

R27 4.7K

D1

1N4148

12

R5 33

R24 220

R4 33

+

C610uF

R18

4.7K