CURRICULUM VITAE

K.SATHISH Email:ksathish.pd@gmail.com Contact: +919949311351

Objective:Dedicated professional seeking suitable position that would enable me to broaden my current skills and challenge my various abilities in ASIC Physical Design.

Professional Experience:

1+ years of experience in the domain of ASIC Physical design. Trained in ASIC - PHYSICAL DESIGN at Institute of Silicon SystemsSummary: Worked on Physical Design including Floorplaning, Placement, CTS, Routing, SI analysis and closure, Timing Closure and Physical Verification

Handled 65nm, 90nm and 130nm technology designs

Expertise in complete PD flow Good understanding of LOW-POWER techniqes Basic knowledge in scripting languages Good knowledge in custom transistor level designTools: Synthesis

RTL Compiler

Place and Route SOC Encounter Parasitic Extraction QRC

Crosstalk Analysis

Celtic

Static Timing Analysis ETS HDL Languages:

Verilog Scripting Languages TCL ACADAMICS

Bachelor of Technology in Electronics & Communication Engineering from JNTU Hyderabad with 70.41% during 2007-2011.

XII from Board of Intermediate Education with 87% during 2004-2006.

SSC from Siddhartha Vidyalayam with 91.5% during 2003-2004.

Projects:

Block I: Description

Technology Node

: 90nm, 5 LM EDA Tools

: SOC Encounter, QRC,ETS STD cell Instance/Gate count

: 50K/750K Hard Macros

: 18 Frequency

: 300 MHz Clock Count

: 2Responsibilities

Timing Closure of the Block including pre PNR checks, Floor Planning, CTS, Post Route Optimization, Fixing DRC and Connectivity issues in PNR level & Implementing Timing ECOs from the signoff .Block II: Description

Technology Node

: 90nm, 5LM EDA Tools

: SOC Encounter, QRC, ETS STD cell Instance/Gate count

: 25K/500K Hard Macros

: 0 Frequency

: 200 MHz Clock Count

: 4

Responsibilities

Timing Closure of the Block including pre PNR checks, Floor Planning, CTS, Post Route Optimization, Fixing DRC and Connectivity Issues in PNR level & Implementing Timing ECOs from the signoff .

Fixing congestion & Timing is critical for this block.

With initial trail runs generated the scaling factors & timing co-relation for PNR & ETS.

Block III: Description Technology Node

: 130nm, 5LM EDA Tools

: SOC Encounter STD cell Instance/Gate count

: 27K/250K Hard Macros

: 12 Frequency

: 200 MHz Clock Count

: 3Responsibilities

Timing Closure of the Block including pre PNR checks ,Floor Planning, CTS, Post Route Optimization, Fixing DRC and Connectivity Issues in PNR levelPCI_DATA Objective

:Timing driven layout Tools

:SOC Encounter Gate count / Area:128,961 / 1,572,915 um2 Macros / STD Cells:12 / 24,450 No. of Clocks

:4 Frequency

:149.9 MHz Utilization

:52.1 % Technology / Layers:TSMC 0.18 microns / 5 Metal LayersResponsibility: Responsible for Floor planning, Power planning, End Cap Placement, Placement Driven Synthesis, Post placement Timing closure, Clock Tree Synthesis, Post clock Timing closure, clock slew fixing, Late mode optimization (Set-up Fixing on prewired database), Early mode optimization (Hold fixing on prewired database), Detailed Routing, Post Route Timing Fixes, Fixing DRCs Checks, antenna fixing.Logic Synthesis

Project 1: An 8-bit synchronous counter with asynchronous reset.

Clocks / Frequency:2/200MHzRole:

Generated Constraint file, TCL file. Performed Wire load and Zero Wire load model. Project 2: A 256-bit counter

Role:

Generated Constraint file.

Calculated clock period for both wireload and zero wire load models Compared the results Declaration:I hereby declare that the information that is provided above is up to date and true.

Place:Date:

(SATHISH.K)