Kingfisher Instruction Manual - Raptor Photonics · Kingfisher Instruction Manual Document number...

Kingfisher Instruction Manual ��

Document number Revision File name Date Page

2013-10-29-01 2.0 Kingfisher_IM_V2_0.doc 07/03/14 1 of 35

This document is the property of Raptor Photonics and must not be copied, shown or in any way be communicated to persons other than those requiring the information for the execution of their duty.

Project designation

Kingfisher Scientific CCD Camera

Document title

Instructions and manual of use

DOCUMENT VALIDATION

Name Title Date

Prepared Chris Davis Raptor Photonics 29th

October 2013 Reviewed Reviewed Reviewed Reviewed Reviewed Approved Authorized

DOCUMENT CHANGE RECORD

Issue Change order Date Pages affected Comment

1.0 17th April 2013 Draft

1.1 29th Oct 2013 Merged with Eagle V spec. Comms protocol and user interface changed. Readout modes and control registers

changed to reflect Eagle V.

1.2 30th Oct 2013 23 Fixed typo for ROI registers and added command for disabling the microprocessor.

1.3 4th Nov 2013 23,25 Added extra info for set/get readout mode.

1.4 6th Nov 2013 Added Binning rates

2.0 7th Mar 2014 Renamed file to match new Project name, removed Draft

watermark for full release.

TABLE OF CONTENTS

1 SCOPE ...................................................................................................................... 5

2 DESIGN OVERVIEW ................................................................................................. 6

2.1 Mechanical Profile ............................................................................................... 6

2.1.1 Lens Mount ................................................................................................... 7

2.1.2 CCD Active Area ........................................................................................... 7

2.2 Physical Interfaces (Standard Product) ............................................................... 8

2.2.1 Camera link connector (3M, Part no. 12226-5150-00FR) ............................. 8

2.2.2 Power & Trigger ............................................................................................ 8

2.2.3 Power (HiRose, Part no. HR10-7R-4P) ........................................................ 8

2.2.4 Trigger In (50ohm SMA) ............................................................................... 9

2.2.5 Trigger out, Exposure (50ohm SMA) ............................................................ 9

2.2.6 Trigger out, Read out (50ohm SMA) ............................................................. 9

2.3 Physical Interfaces (OEM Product) ................................................................... 10

2.3.1 Camera link connector (3M, Part no. 12226-5150-00FR) ........................... 10

2.3.2 Power & Trigger (3M, Part no. N2510-6002-RB) ........................................ 10

2.3.3 Power Specification & TEC Cooling ............................................................ 10

2.4 Digital Video out ................................................................................................ 12

3 CAMERA CONTROL DETAILS .............................................................................. 14

3.1 Micro reset ........................................................................................................ 14

3.2 System state ..................................................................................................... 14

3.3 FPGA control register ....................................................................................... 14

3.4 Frame rate ........................................................................................................ 14

3.5 Exposure ........................................................................................................... 15

3.6 Trigger Modes ................................................................................................... 15

3.6.1 Idle mode .................................................................................................... 15

3.6.2 Internal Trigger ........................................................................................... 15

3.6.3 External Trigger .......................................................................................... 16

3.6.4 Snapshot trigger ......................................................................................... 17

3.6.5 Trigger Abort ............................................................................................... 17

3.7 ROI ................................................................................................................... 17

3.8 Binning .............................................................................................................. 18

3.9 Binning and ROI ................................................................................................ 19

3.10 Pixel readout rate .............................................................................................. 19

3.11 Readout Mode .................................................................................................. 19

3.12 Test Pattern Image ........................................................................................... 19

3.13 Unit Serial number ............................................................................................ 20

3.14 Manufacturers Data .......................................................................................... 21

3.14.1 ADC calibration data (Sensor temp) ........................................................... 21

3.14.2 DAC calibration data ................................................................................... 22

4 SERIAL COMMUNICATION (CAMERALINK INTERFACAMERALINK INTERFACAMERALINK INTERFACAMERALINK INTERFACECECECE) .................................... 23

4.1 Overview ........................................................................................................... 23

4.2 ETX/ERROR codes .......................................................................................... 24

4.3 Set Commands ................................................................................................. 25

4.4 Query Commands ............................................................................................. 27

4.5 Serial Command Examples............................................................................... 30

4.5.1 Set System status (Enable Command Ack and Check sum mode) ............ 30

4.5.2 Get System Status ...................................................................................... 30

4.5.3 Get Micro version ........................................................................................ 30

4.5.4 Get FPGA version ....................................................................................... 30

4.5.5 Reset camera ............................................................................................. 30

4.5.6 Read Sensor PCB temperature .................................................................. 31

4.6 Serial Command Error Examples ...................................................................... 31

4.6.1 Missing or wrong checksum........................................................................ 31

4.6.2 Partial host command with missing data/ETX/checksum ............................ 31

4.6.3 Corrupt/Unknown host command ............................................................... 31

APPENDIX A - FPGA FIRMWARE UPLOAD ............................................................... 32

Figure 1: SolidWorks model - camera assembly ............................................................... 6

Figure 2: Mechanical profile drawing/ Connection details. ................................................ 7

Figure 3: 26 pin 3M SDR Connector ................................................................................. 8

Figure 4: Digital Video Timing ......................................................................................... 13

Figure 5: External Trigger timing ..................................................................................... 16

Figure 6: ROI size and offset ........................................................................................... 18

Figure 7: Example frame rates with binning .................................................................... 19

1 SCOPE

This document provides detailed instructions for the operation of the Kingfisher, Scientific CCD

camera. Details of the camera electrical interfaces and communication protocols are also provided.

Both the Kingfisher674 and the Kingfisher694 are detailed.

2 DESIGN OVERVIEW

2.1 Mechanical Profile

Figure 1: SolidWorks model - camera assembly

units are in mm [ inches]

Feature Description

1 12V power connector, HiRose Part no.

2 TTL Trigger input, 50ohm SMA

3 Label recess, Model No./Serial number

4 TTL Trigger output, 50ohm SMA (Exposure)

5 TTL Trigger output, 50ohm SMA (Readout)

6 Camera link (Base) SDR, 3M, Part no. 12226-5150-00FR

Figure 2: Mechanical profile drawing/ Connection details.

2.1.1 Lens Mount

The camera has a C-mount lens thread. The thread is 1.000 inch (25.4 mm) in diameter, with 32

threads per inch, designated as "1-32 UN 2A" in the ANSI B1.1 standard for unified screw

threads. The focal distance is 17.526 millimetres (0.6900 in) for a C mount.

2.1.2 CCD Active Area

The ICX674 sensor has an active area of 8.8076mm*6.6284mm.

The ICX694 sensor has an active area of 12.521mm*10.024mm.

1

2

4

5

6

3

2.2 Physical Interfaces (Standard Product)

2.2.1 Camera link connector (3M, Part no. 12226-5150-00FR)

The camera uses a camera link shrunk Delta Ribbon (SDR) 26 way connector. The pin-out is

shown below.

Figure 3: 26 pin 3M SDR Connector

2.2.2 Power & Trigger

2.2.3 Power (HiRose, Part no. HR10-7R-4P)

For the 12V power input connection a 4 way HiRose connector is used. The part number of this

connector is HR10-7R-4P. The corresponding socket connector part number is HR10-7P-4S. The

pin out of the connector is detailed in the table below.

Pin Number Connection

1,2 12V

3,4 GND

2.2.4 Trigger In (50ohm SMA)

External synchronisation of the start of integration signal may be achieved using the Trigger IN

connector. Input impedance = 510ohms, 200pF input capacitance. Input logic levels are;

- Logic HIGH >2.31V

- Logic Low <0.99V

Min. pulse width = 100ns

2.2.5 Trigger out, Exposure (50ohm SMA)

For all camera modes the Trigger output, Exposure SMA, will represent the integration period of

the sensor. The trigger output signal will be a TTL output pulse. The signal will remain low (0V)

and then be driven high during the integration period.

The source impedance will be equal to 50ohms.

2.2.6 Trigger out, Read out (50ohm SMA)

For all modes of the camera the Trigger output, Read out SMA, will represent the duration of the

CCD readout. The trigger output signal will be a TTL output pulse. The signal will remain low

(0V) and then be driven high during the read out period of the CCD.

The source impedance will be equal to 50ohms.

2.3 Physical Interfaces (OEM Product)

2.3.1 Camera link connector (3M, Part no. 12226-5150-00FR)

See section 2.2.1 for details.

2.3.2 Power & Trigger (3M, Part no. N2510-6002-RB)

A 10 way 3M connector is used to provide power and trigger connections to the camera. The part

number of this connector is N2510-6002-RB, the corresponding receptacle connector part number

is 8510-4500PL. The pin out of the connector is detailed in the below.

Three trigger IOs are provided on the 10 way 3M connector.

One trigger input is provided on pin 8 (TRIG_TC_CONN), this pin as a termination impedance of

510ohms and load of approximately 200pF.

Two TTL output signals are provided on pins 6 and 10. The trigger on pin 6

(TRIG_TFG_CONN) will indicate the exposure time whereas the trigger on pin 10

(TRIG_OUT_CONN) will indicate the readout time. Both these outputs have a source impedance

of 51ohms. They are capable of sinking and sourcing 32mA and will have an output voltage of

3V3. The signals will remain low (0V) and then be driven high during the integration period and

the readout time respectively.

The 12V power input connections are found on pins 1&2 with the GND return connections being

found on pins 3,4,5,7 & 9 of the 10 way connector.

Pin Number Connection

1,2 12V

3,4,5,7,9 GND

2.3.3 Power Specification & TEC Cooling

Unit input power specification is 12V +/- 10% with a maximum of 8Watts power dissipation with

the TEC cooler switched off.

The camera electronics have provision to drive a Thermoelectric Cooler (TEC) to cool the CCD.

The OEM Product will have no TEC fitted.

The Standard Product camera will have a TEC fitted. The camera will attempt to drive the TEC to

achieve a delta T of approximately 10C from the ambient.

Additional inrush current (peak power) is required when the cooler power is switched from low to

high. Peak power <= 15Watts. The total, maximum steady state, unit power dissipation is

15Watts.

2.4 Digital Video out

The Kingfisher camera produces mono, digital video output. A camera link strobe clock of

20MHz is used with 16bit data and 1 tap output, i.e. Base camera link. Output signals comply with

the Camera Link Standard (Ref. http://www.visiononline.org/vision-standards-

details.cfm?id=37&type=6)

The Kingfisher hardware has been designed to enable it to clock several variants of SONY’s ICX

series sensors. Currently the ICX674 and ICX694 sensors are supported.

The ICX674 has 1940*1460 active pixels whereas the ICX694 has 2758*2208 active pixels.

Camera link signals and pixel order as shown below.

FVAL is held high for the duration of a valid frame read out

LVAL is held high for the duration of a valid line read out and will go low before/after each valid

line

DVAL will only go high for valid pixels during a line read out, and will stay high for the duration

of a 20MHz clock period. For 20MHz readout mode DVAL will be held high for the duration of a

valid line. Ie every pixel is valid.

Logic levels are as per camera link standard.

Figure 4: Digital Video Timing

FVPERIOD = Frame Valid period, Variable see FVhigh + exposure time*

FVHIGH = Variable depending of Readout speed, Binning and ROI*

LVSTART = Variable depending of Readout speed, Binning and ROI*

LVHIGH = Variable depending of Readout speed, Binning and ROI*

LVLOW = Variable depending on Binning.*

*Note: Exact timings required to be defined.

Image Latency is not more than1 line period

The Kingfisher camera has been tested and verified on EPIX PIXCI EL1, EB1, E4 and E8 camera

link frame grabber cards.

LVSTART LVLOW

LVHIGH FVAL

LVAL 2 3 Ysize-1 Ysize 1

FVHIGH FVPERIOD

DVAL

CH1

data

X X 1

Pixel no.

1 2

2 X

DVAL/

Pixel No.

CH1 data/

Pixel No.

3 CAMERA CONTROL DETAILS

3.1 Micro reset

The camera contains an internal microcontroller that is used to process serial commands from the

host. The micro controller can be reset by sending a reset command. The micro will take approx.

100msec to reset.

The host can poll the camera with a Get system status command until a valid response is received.

3.2 System state

The system state register is used to control the serial communications mode and enable access to

the on board EPROM for programming and reading system information.

The system state register may also be used to reset the FPGA or hold the FPGA in reset. Note than

when reset is released the FPGA will take approx. 500msecs to reboot. Once the FPGA has booted

it will take approx. 5secs for the FPGA to load and fully apply the correction map for each pixel.

3.3 FPGA control register

The FPGA control register is used to switch the cooling ON/OFF.

See section 3.14.2 for more information on the TEC drive option.

3.4 Frame rate

When internal trigger and fixed frame rate have been selected the Frame rate registers are used to

select the required frame rate. A 40 bit register is used to hold the frame rate value with each count

equal to 50nsecs (i.e. 1/20MHz). For example;

1frame per second = 20,000,000cnts

1frame per minute = 1,200,000,000cnts

Should the exposure exceed the frame rate period then the exposure will dominate and the frame

rate will be reduced accordingly.

Reserved

Reserved

Reserved Reserved

bit 7 bit 6 bit 5 bit 4

Reserved

bit 3

Reserved

bit 2

Reserved

bit 1

TEC on/off

bit 0

The max frame rate that can be achieved is dependent on the pixel readout rate and the level of

binning in the image. The number of lines is programmable via the vertical and horizontal binning.

For Fixed frame rate mode to calculate the min Frame period in clock cycles.

3.5 Exposure

The exposure registers are used to determine the exposure of the sensor under all triggering

conditions. A 40 bit register is used to hold the exposure value with each count equal to 50nsecs

(i.e. 1/20MHz). Theoretical max exposure = 15.2 hours. In practice the max exposure will be

limited by the dark current of the device.

Once an exposure has started it cannot be interrupted by another trigger. If for example the camera

is in external trigger mode, any trigger pulses applied to the camera during exposure will be

ignored.

An exposure may be aborted by setting the Abort bit the in trigger mode register. Once an

exposure has been aborted the camera will run in the trigger mode selected by the trigger mode

register.

3.6 Trigger Modes

The trigger modes of the camera can be set using the internal trigger mode register. Bits are as

outlined below.

Note that bit3 and bit 0 are self clearing bits.

3.6.1 Idle mode

If the External trigger enable, bit 6, of the Trigger mode register is set = 0 and the Sequence

trigger bit 2 is set = 0, then the camera will remain in idle mode i.e. no images will be read from

the sensor.

3.6.2 Internal Trigger


trigger bit 2 is set = 1, then the camera will use an internal trigger to start the integration and

readout of the sensor. The camera will run with continuous integration and readout of the sensor

Two modes of internal trigger are available Integrate Then Read (ITR) mode and Fixed frame rate

mode.

Ext R/F Ext Trig en Reserved Reserved

bit 7 bit 6 bit 5 bit 4

Abort

bit 3

Seq. trig

bit 2

Fix. frm en

bit 1

Snap Shot

bit 0

If the Fixed frame rate bit 1 = 0 then ITR mode will be used to capture a continuous sequence of

images. The camera will immediately trigger the start of a new integration period when the

previous image has been readout.

If the Fixed frame rate bit 1 = 1 then the camera will generate an internal trigger signal at a user

programmable frame rate.

3.6.3 External Trigger

If the External trigger enable, bit 6, of the Trigger mode register is set = 1 then the camera will use

an external trigger to start the integration and readout of the sensor.

If the External Rising/Falling, bit 7, is set = 1 then the rising edge of an incoming trigger pulse is

used to trigger the start of integration. Else the falling edge is used to trigger the start of

integration, both scenarios are depicted in the diagram below.

Notes;

- Time from Signal received at camera to start of exposure = 1.125us +/-50ns jitter

- External trigger, triggers the start of integration of the sensor

- Min exposure is 1ms

Figure 5: External Trigger timing

Tfp = Frame period

Tpw = Trigger pulse width, min width > one 20MHz clock period

Ts = Delay from falling/rising edge of trigger to start of exposure.

Trd = readout time for 1 progressive frame

Tint = integration time of sensor

Jitter performance = +/- one 20MHz clock period

Etc.

Tpw

Ts

Wait for trig Integration

Trd

Tfp

Wait for trig

Tint

Ts

EXT.

TRIG

(-ve)

EXT.

TRIG

(+ve)

Readout

TRIG

OUT

3.6.4 Snapshot trigger


trigger bit 2 is set = 0, then the camera will remain in idle mode i.e. no images will be read from

the sensor.

Setting bit 0 will trigger an acquisition from the camera. Note that bit 0 is self clearing.

3.6.5 Trigger Abort

For all modes of the camera the Trigger Abort (bit 3) will abort the current exposure when it is set

= 1. Video data will still be sent from the camera. The image sent will be for the duration of the

exposure up until the abort command was received.

Note that bit 3 of the trigger mode register is self-clearing.

3.7 ROI

A region of interest within the main active region of 1940*1460 (2758*2208 Kingfisher694) may

be defined. The ROI is setup using a bank of registers to control the X offset, the ROI width, the

Y offset and the ROI height. These parameters are shown pictorially below.

The user must ensure that X offset + ROI width is ≤ 1940 (2758 for Kingfisher694) and similarly

the Y offset + ROI height is ≤ 1460 (2208 for Kingfisher694). Also ROI width and ROI height

must be > 0.

1460/2208 lines

1940/2758 pixels

X

ROI

W

Y

H

X = ROI X Offset

Y = ROI Y Offset

W = ROI width

H = ROI height

Figure 6: ROI size and offset

It is possible to send a zero value to the ROI height, this will cause the camera to stop imaging

even when a new value of greater than zero is issued. When/If this occurs the ROI height must be

set to a value greater than zero and a Trigger Abort command will then need to be issued to reset

the acquisition sequence. The camera will then trigger and readout as normal.

It is recommended that when the ROI has been changed that the Host re-issues the command to set

the appropriate trigger mode with the 'Trigger Abort' (bit 3) set in the trigger mode register.

Further triggers/commands may be issued after this command.

Note: The Image resolution must be set correctly in the frame grabber format file to ensure

correct display of the data.

3.8 Binning

In addition to standard 1*1 output, various levels of pixel binning may be programmed up to

16*16. Pixel binning is performed on the CCD and asymmetric binning combinations may be used

e.g. 1*2, 2*1, 1*3, 3*1, 4*7 etc.

For values of binning in either the X or the Y direction that do not divide evenly into the total

number of pixels in the X,Y direction. The division fraction will always be rounded up to give the

total number of display pixels for a given bin level.

e.g. XBIN = 7, gives 1940/7 = 277.14 =>278 horizontal display pixels, note that the last column

will not contain the full bin of 7 pixels but will contain a bin of the remaining active pixels.

For unbinned image data, pixel readout rates of 20MHz, 5MHz and 1MHz are available.

Combinations of Horizontal and vertical binning may be used to increase the frame rate.

For minimum exposure example minimum frame periods, maximum frame rates, are given below;

ICX674

Frame Rate (Hz)

BIN 20MHz Pixel clock 5MHz Pixel clock 1MHz Pixel clock

1*1 6.2 1.7 0.4

2*2 11.5 4.2 1.3

4*4 20.1 9.3 3.9

8*8 32.1 18.2 10.9

16*16 45.4 30.2 22.2

ICX694

Frame Rate (Hz)

BIN 20MHz Pixel clock 5MHz Pixel clock 1MHz Pixel clock

1*1 TBD TBD TBD

2*2 TBD TBD TBD

4*4 TBD TBD TBD

8*8 TBD TBD TBD

16*16 TBD TBD TBD

Figure 7: Example frame rates with binning

Note: The Image resolution must be set correctly in the frame grabber format file to ensure

correct display of the data.

3.9 Binning and ROI

Binning and ROI may be active simultaneously. The ROI is determined on a single pixel basis

after which Binning may be applied.

3.10 Pixel readout rate

A pixel readout rate of 20 MHz, 5MHz or 1MHz may be selected.

A pixel readout of 20MHz provides the shortest full frame readout time.

A pixel readout rate of 1MHz provides the lowest readout noise for the camera.*

*Note that for readout rates below 20MHz the sensor needs to be cooled to ~0C to achieve

optimum performance.

3.11 Readout Mode

The camera can be configured to output the digitised video data in a number of ways. The raw

CDS (correlated digital sample) from the sensor is the default output. A second output which

provides a clamped baseline version of the CDS sensor data is also available.

3.12 Test Pattern Image

For all readout modes of the camera a test pattern image may be read from the camera instead of

CCD data. The test image will consist of a fixed ramp pattern that will start with a value of 0 on

the 1st pixel read from the camera and increment by one for each subsequent pixel read from the

camera.

3.13 Unit Serial number

The camera serial number may be read from the camera’s EPROM when the Comms is enabled to

the EPROM. Two bytes are used to hold the units serial number.

Note that the serial number may also be read as part of the Manufacturers data.

3.14 Manufacturers Data

Manufacturer’s data may be read from the camera’s EPROM when the Comms is enabled to the

EPROM. 18 bytes are used to hold the manufacturers data that includes the serial number.

Starting at address 0x000002

2 bytes Serial number

3 bytes Build Date (DD/MM/YY)

5 bytes Build code (5 ASCII chars)

2 bytes ADC cal 0degC point

2 bytes ADC cal+40degC point

2 bytes DAC cal 0degC point

2 bytes DAC cal+40degC point

3.14.1 ADC calibration data (Sensor temp)

Two ADC values are held in the EPROM, each ADC value is held in 2bytes of the EPROM. The

two ADC values represent the imaging sensor temperature at 0 degrees centigrade and +40

degrees centigrade. The ADC reading will vary linearly with temperature and the two calibration

points may be used to define a straight line that can be used to convert the ADC reading to degrees

centigrade.

The temperature of the CCD is determined from a platinum resister attached to the CCD. The

voltage across the resistor varies linearly with temperature. This voltage is read via an Analogue to

Digital (ADC) converter.

For calibration two ADC count values for the CCD temperature are determined during

qualification testing for each camera i.e. at 0degC and at +40degC. These two points are stored in

the cameras EPROM. A straight line graph can then be used to determine temperature for any

given ADC count value.

Straight line eqn. Y = M*X+C, becomes

where the slope, M = (Y1-Y2)/(X1-X2) -- two known points from calibration

Constant offset, C = Y2 - M*(X2)

For any ADC value, ADC temp.(degC) = M*(ADC counts) + C

For example, the calibration values below give a straight line graph as shown.

ADC cal. 0degC = 1226 counts, ADC cal. +40degC = 788 counts

In the above example a reading from the ADC of 1062 counts would equate to +15degC

3.14.2 DAC calibration data

A Digital to Analogue converter(DAC) is used to produce a voltage for the set point of the TEC

control loop. Two values are determined for 0degC and +40degC for each camera during

qualification testing and stored in the cameras EPROM.

The relationship of DAC counts to set point temperature is linear and therefore a straight line

graph can be used to determine the set point temperature from the DAC count value.

4 SERIAL COMMUNICATION (CAMERALINKCAMERALINKCAMERALINKCAMERALINK INTERFACEINTERFACEINTERFACEINTERFACE)

4.1 Overview

For version 2.3 of the Micro firmware, the Power on default settings for camera serial port are;

- 115200 baud

- 1 start bit

- 8 data bits

- 1 stop bit

UART message format from Host to camera

Command Data 1 Data 2 ........ Data n ETX Chk_Sum

The first Byte is the command to the Microcontroller in the camera, following bytes contain data

required by the command, the ETX byte terminates the command. 0x50 is always used to

terminate the command. An additional check sum byte may also be required to be sent by the host

if check sum mode is enabled.

UART message format from camera to Host

Data 1 Data 2 ........ Data n ETX Chk_Sum

all or none of the above bytes may be sent in response to commands from the host depending on

the commands sent by the host.

An optional mode of operation is included in the firmware for command acknowledge. Once

enabled the camera will respond to all commands send by the host. After the camera has received

and processed the command from the host, a single command acknowledge byte will be sent at the

end of transmission (ETX). i.e. should the host command require data to be sent from the camera

then the ETX byte will be sent at the end of the requested data.

Another optional mode of operation is included in the firmware is for check sum operation, this

mode should only be used when the command acknowledge mode is enabled. Once the check sum

mode is enabled the camera will only act upon commands that are received with the correct check

sum byte sent at the end of the command packet. Note that if the check sum feature is not enabled

check sum bytes may still be sent at the end of a command packet, the command will be processed

and the check sum will be ignored. The check sum byte should be the result of the Exclusive OR

of all bytes in the Host command packet including the ETX byte.

When check sum mode is enabled data returned from the camera will include an echo of the

checksum from the host command

By default the camera will boot up with both command acknowledge and check sum operation

disabled.

It is intended that the camera be operated from a higher level perspective whereby complete

UART messages or groups of UART messages are used to achieve required camera functionality.

Bits in registers that have not been identified in the documentation should be ignored.

Once a command has been received by the camera all subsequent commands from the host will be

ignored until the command has been processed.

It is recommend that both command acknowledge and check sum operation be enabled at power

up.

4.2 ETX/ERROR codes

Error codes will be sent as ETX characters by the camera in response to commands that have

failed.

0x50 ETX Command acknowledge, command processed successfully.

0x51 ETX_SER_TIMEOUT Partial command packet received, camera timed out waiting for

end of packet. Command not processed

0x52 ETX_CK_SUM_ERR Check sum transmitted by host did not match that calculated for

the packet. Command not processed

0x53 ETX_I2C_ERR An I2C command has been received from the Host but failed

internally in the camera.

0x54 ETX_UNKNOWN_CMD Data was detected on serial line, command not recognized

0x55 ETX_DONE_LOW Host Command to access the camera EPROM successfully

received by camera but not processed as EPROM is busy. i.e.

FPGA trying to boot.

4.3 Set Commands

Set Command Serial Packet Comments

Micro RESET 0x55 0x99 0x66 0x11 0x50 0xEB

Will trap Micro causing watchdog and

reset of firmware. The camera will give

no response to this command

Set system state 0x4F 0xYY 0x50

8 bit value YY

Bit 7 = Reserved

Bit 6 = 1 check sum mode enabled

Bit 5 = Reserved

Bit 4 = 1 to enable command ACK

Bit 3..2 = Reserved

Bit 2 = 1 if FPGA booted ok

Bit 1 = 0 to Hold FPGA in RESET

Bit 0 = 1 to enable comms to FPGA

EPROM

Set FPGA CTRL reg 0x53 0xE0 0x02 0x00 0xYY 0x50 YY Bit 7,6,5,4,3,2,1 = reserved

YY Bit 0 = 1 to enable TEC (Default=1)

Set Frame rate

(Internal trigger,

fixed rate only)

0x53 0xE0 0x02 0xDC 0xY1 0x50

0x53 0xE0 0x02 0xDD 0xY2 0x50

0x53 0xE0 0x02 0xDE 0xY3 0x50

0x53 0xE0 0x02 0xDF 0xY4 0x50

0x53 0xE0 0x02 0xE0 0xY5 0x50

40 bit value, 5 separate commands,

1 count = 1*20MHz period =50nsecs

Y1 = MSB of 5 byte word

:

Y5 = LSB of 5 byte word;

Frame rate updated on LSB write

Set Exposure

0x53 0xE0 0x02 0xED 0xY1 0x50

0x53 0xE0 0x02 0xEE 0xY2 0x50

0x53 0xE0 0x02 0xEF 0xY3 0x50

0x53 0xE0 0x02 0xF0 0xY4 0x50

0x53 0xE0 0x02 0xF1 0xY5 0x50

40 bit value, 1count = 1*20MHz period

Y1 = MSB of 5 byte word

:::

Y5 = LSB of 5 byte word;

Frame rate updated on LSB write

Set Trig Mode 0x53 0xE0 0x02 0xD4 0xYY 0x50

YY Bit 7 = 1 to enable rising edge, = 0

falling edge Ext trigger (Default=1)

YY Bit 6 = 1 to enable External trigger

(Default=0)

YY Bit 3 = 1 to Abort current exposure,

self clearing bit (Default=0)

YY Bit 2 = 1 to start continuous seq'., 0 to

stop (Default=1)

YY Bit 1 = 1 to enable Fixed frame rate, 0

for continuous ITR (Default=0)

YY Bit 0 = 1 for snapshot, self clearing

bit (Default=0)

Set TEC set point 0x53 0xE0 0x02 0xFB 0xMM 0x50

0x53 0xE0 0x02 0xFA 0xLL 0x50

12 bit DAC value, LSB = LL byte, Lower

nibble of MM = MSBs

Reg 0xFB, bits 3..0 = set point bits 11..8

Reg 0xFA, bits 7..0 = set point bits 7..0

12 bit value to be converted to

temperature (see "Get manufacturers

Data" section 3.14)

Set ROI X Size 0x53 0xE0 0x02 0xB4 0xMM 0x50

0x53 0xE0 0x02 0xB5 0xLL 0x50

12bit value

MM bits 3..0 = size bits 11..8

LL bits 7..0 = size bits 7..0

Data updated on write to LSBs

Set ROI X offset 0x53 0xE0 0x02 0xB6 0xMM 0x50

0x53 0xE0 0x02 0xB7 0xLL 0x50

12bit value

MM bits 7..0 = offset bits 15..8

LL bits 7..0 = offset bits 7..0


Set ROI Y Size 0x53 0xE0 0x02 0xB8 0xMM 0x50

0x53 0xE0 0x02 0xB9 0xLL 0x50

12bit value




Set ROI Y offset 0x53 0xE0 0x02 0xBA 0xMM 0x50

0x53 0xE0 0x02 0xBB 0xLL 0x50

12bit value




Set X Binning 0x53 0xE0 0x02 0xA1 0xYY 0x50

YY Default = 0x00

YY = 0x00, X binning *1

YY = 0x01, X binning *2

:

YY = 0x0F, X binning *16

Set Y Binning 0x53 0xE0 0x02 0xA2 0xYY 0x50

YY Default = 0x00

YY = 0x00, Y binning *1

YY = 0x01, Y binning *2

:

YY = 0x0F, Y binning *16

Set pixel readout

clock

0x53 0xE0 0x02 0xA3 0xY1 0x50

0x53 0xE0 0x02 0xA4 0xY2 0x50

20MHz Y1=0x01,Y2=0x01 (Default)

5MHz Y1=0x04,Y2=0x02

1MHz Y1=0x12, Y2=0x10

Set readout mode 0x53 0xE0 0x02 0xF7 0xYY 0x50

YY = 0x00 , Baseline Clamped Data

YY = 0x01 , CDS Data (Default)

YY = 0x04 , Test pattern enabled

Micro Disable 0x54 0x50 Micro disable command should be sent at

the end of every transmission block.

4.4 Query Commands

Query Command Send Serial Packet Comments

Get system status 0x49 0x50

1 byte returned from camera

Bit 7 = Reserved

Bit 6 = 1 check sum mode enabled

Bit 5 = Reserved

Bit 4 = 1 to enable command ACK

Bit 3..2 = Reserved

Bit 2 = 1 if FPGA booted ok

Bit 1 = 0 to Hold FPGA in RESET

Bit 0 = 1 to enable comms to FPGA

EPROM

Get FPGA Status

0x53 0xE0 0x01 0x00 0x50

0x53 0xE1 0x01 0x50

1 byte returned from camera

Bit 7,6,5,4,3,2,1 = reserved

Bit 0 = 1 to enable TEC (Default=1)

Get Frame rate

(Internal trigger,

fixed rate only)

0x53 0xE0 0x01 0xDC 0x50

0x53 0xE1 0x01 0x50

0x53 0xE0 0x01 0xDD 0x50

0x53 0xE1 0x01 0x50

0x53 0xE0 0x01 0xDE 0x50

0x53 0xE1 0x01 0x50

0x53 0xE0 0x01 0xDF 0x50

0x53 0xE1 0x01 0x50

0x53 0xE0 0x01 0xE0 0x50

0x53 0xE1 0x01 0x50

40 bit value, internal registers DC to

E0 read, register E0 contains the LSBs

1 count = 1*20MHz period = 50nsecs

Get Exposure

0x53 0xE0 0x01 0xED 0x50

0x53 0xE1 0x01 0x50

0x53 0xE0 0x01 0xEE 0x50

0x53 0xE1 0x01 0x50

0x53 0xE0 0x01 0xEF 0x50

0x53 0xE1 0x01 0x50

0x53 0xE0 0x01 0xF0 0x50

0x53 0xE1 0x01 0x50

0x53 0xE0 0x01 0xF1 0x50

0x53 0xE1 0x01 0x50

40 bit value, internal registers ED to

F1 read, register F1 contains the LSBs

1 count = 1*20MHz period = 50nsecs

Get Trig Mode 0x53 0xE0 0x01 0xD4 0x50

0x53 0xE1 0x01 0x50

1 byte returned;

Bit 7 = 1 rising edge trig enabled

Bit 6 = 1 External trigger enabled

Bit 5,4 = reserved

Bit 3 = Always read as '0'

Bit 2 = 1 continuous seq'., enabled

Bit 1 = 1 Fixed frame rate enabled, 0

for continuous ITR

Bit 0 = Always read as '0'

Get TEC set point 0x53 0xE0 0x01 0xFB 0x50

0x53 0xE1 0x01 0x50

12 bit DAC value,

Reg 0xFB, bits 3..0 = set point bits

0x53 0xE0 0x01 0xFA 0x50

0x53 0xE1 0x01 0x50

11..8

Reg 0xFA, bits 7..0 = set point bits

7..0

12 bit value to be converted to

temperature (see " Get manufacturers

Data" section 3.14)

Get X Binning 0x53 0xE0 0x01 0xA1 0x50

0x53 0xE1 0x01 0x50

1 byte returned;

= 0x00, X binning *1 (Default)

= 0x01, X binning *2

:

= 0x0F, X binning *16

Get Y Binning 0x53 0xE0 0x01 0xA2 0x50

0x53 0xE1 0x01 0x50

1 byte returned;

= 0x00, Y binning *1 (Default)

= 0x01, Y binning *2

:

= 0x0F, Y binning *16

Get pixel readout

clock

0x53 0xE0 0x01 0xA3 0x50

0x53 0xE1 0x01 0x50

0x53 0xE0 0x01 0xA4 0x50

0x53 0xE1 0x01 0x50

2 bytes returned;

1st byte from register 0xA3 => Y1

2nd

byte from register 0xA4 => Y2

20MHz Y1=0x01,Y2=0x01 (Default)

5MHz Y1=0x04,Y2=0x02

1MHz Y1=0x12, Y2=0x10

Get readout mode 0x53 0xE0 0x01 0xF7 0x50

0x53 0xE1 0x01 0x50

1 byte returned;

= 0x00 , Baseline Clamped Data

= 0x01 , CDS Data (Default)

= 0x04 , Test pattern enabled

Get PCB temperature

0x53 0xE0 0x02 0x70 0x00 0x50

0x53 0xE1 0x01 0x50

0x53 0xE0 0x02 0x71 0x00 0x50

0x53 0xE1 0x01 0x50

2 bytes returned for 12 bit signed value

1st byte => bits 3..0 = MSBs 11..8

2nd

byte => bits 7..1 = LSBs 7..0

Divide 12 bit value by 16 to get temp.

Get CCD silicon

temperature

0x53 0xE0 0x02 0x6E 0x00 0x50

0x53 0xE1 0x01 0x50

0x53 0xE0 0x02 0x6F 0x00 0x50

0x53 0xE1 0x01 0x50

2 bytes returned, MSB followed by

LSB, indicate sensor reading(Therm).

Conversion formula to deg C see

section 3.14

Get Micro version 0x56 0x50 2 bytes returned. 1

st byte Major

version 2nd

byte Minor version.

Get FPGA version

0x53 0xE0 0x01 0x7E 0x50

0x53 0xE1 0x01 0x50

0x53 0xE0 0x01 0x7F 0x50

0x53 0xE1 0x01 0x50

Set address 7E (Major Version Byte)

Read address 7E, 1 byte

Set address 7F (Minor Version Byte)

Read address 7F, 1 byte

Get Unit Serial

Number

0x53 0xAE 0x05 0x01 0x00 0x00

0x02 0x00 0x50

0x53 0xAF 0x02 0x50

2 bytes returned 1st byte is the LSB 2

nd

is the MSB

Get manufacturers

Data

0x53 0xAE 0x05 0x01 0x00 0x00

0x02 0x00 0x50

Get 18 bytes from cameras EPROM.

For 2 byte values 1st byte returned is

0x53 0xAF 0x12 0x50

the LSB.

Starting at address 0x000002

2 bytes Serial number

3 bytes Build Date (DD/MM/YY)

5 bytes Build code (5 ASCII chars)

2 bytes ADC cal 0degC point

2 bytes ADC cal+4 0degC point

2 bytes DAC cal 0degC point

2 bytes DAC cal+4 0degC point

4.5 Serial Command Examples

NOTE: Assume that Command Ack and Check sum mode are enabled unless otherwise

stated

4.5.1 Set System status (Enable Command Ack and Check sum mode)

From power up

Command TX bytes (to camera) RX’d bytes (From camera)

Set System status (=0x56) 0x4F 0x56 0x50 0x49 0x50 0x49 (ack + chk_sum)

YY Bit 7= 0 - reserved

YY Bit 6= 1 to enable check sum mode

YY Bit 5= 0 to enable external comms

YY Bit 4 = 1 to enable command ack

YY Bit 3 = 0 - reserved

YY Bit 2 = 1 - reserved

YY Bit 1 = 1 FPGA NOT in RESET

YY Bit 0 = 0 to disable comms to FPGA EPROM

4.5.2 Get System Status


Get system status 0x49 0x50 0x19 0x56 0x50 0x19 (status = 0x56)

4.5.3 Get Micro version


Get Micro version 0x56 0x50 0x06 0x02 0x03 0x50 0x06 (V2.3)

4.5.4 Get FPGA version


Get FPGA version

0x53 0xE0 0x01 0x7E 0x50

0x9C 0x50 0x9C

0x53 0xE1 0x01 0x50 0xE3 0x01 0x50 0xE3

0x53 0xE0 0x01 0x7F 0x50

0x9D 0x50 0x9C

0x53 0xE1 0x01 0x50 0xE3 0x0B 0x50 0xE3 (v1.11)

4.5.5 Reset camera


Micro Reset 0x55 0x99 0x66 0x11 0x50

0xEB None

Set system State to Hold

FPGA in RST -- Poll camera

with this command every

500msecs until Rx bytes

received

0x4F 0x51 0x50 0x4E

(0x50 0x4E) received when

Micro has re-booted

successfully

Set system State to boot the 0x4F 0x52 0x50 0x4D 0x50 0x4D

FPGA

Get system status -- Poll the

camera with this command

every 500ms until bit 2 of

the received status indicates

that the FPGA has booted

ok.

0x49 0x50 0x19

(0x52 0x50 0x19) -- FPGA not

booted

(0x56 0x50 0x19) -- FPGA

booted ok.

4.5.6 Read Sensor PCB temperature


Get PCB temperature

0x53 0xE0 0x02 0x70 0x00

0x50 0x91 0x50 0x91

0x53 0xE1 0x01 0x50 0xE3 0x01 0x50 0xE3

0x53 0xE0 0x02 0x71 0x00

0x50 0x90 0x50 0x90

0x53 0xE1 0x01 0x50 0xE3 0x93 0x50 0xE3 (25.18degC)

4.6 Serial Command Error Examples

NOTE: Assume that Command Ack and Check sum mode are enabled unless otherwise

stated

4.6.1 Missing or wrong checksum


Get system status 0x49 0x50 0x52 0x19

Camera has received a partial command but not received the correct check sum and therefore

responds with an error code of 0x52 + sends the check sum byte that it had been expecting. The

command is ignored.

4.6.2 Partial host command with missing data/ETX/checksum


Get system status 0x49 0x51 0x19

Camera has received a partial command but not received expected data or the ETX character.

Camera responds with error code 0x51 + sends the check sum byte that it had been expecting. The

command is ignored.

4.6.3 Corrupt/Unknown host command


Get system status 0x48 0x50 0x19 0x54 0x48

1st byte is corrupt and the camera has received an unknown command. Camera responds with

error code 0x54 + sends the check sum byte that it had been expecting. The command is ignored.

APPENDIX A - FPGA FIRMWARE UPLOAD

CAMERA EPROM

The cameraEPROM is divided into15 sectors with address spaces as outlined below. Note that

each address points to a 16bit word.

/* Sector Structure... Sector Kwords words start end start end 1 4 4096 0 4095 000000 000FFF 2 4 4096 4096 8191 001000 001FFF 3 4 4096 8192 12287 002000 002FFF 4 4 4096 12288 16383 003000 003FFF 5 4 4096 16384 20479 004000 004FFF 6 4 4096 20480 24575 005000 005FFF 7 4 4096 24576 28671 006000 006FFF 8 4 4096 28672 32767 007000 007FFF 9 32 32768 32768 65535 008000 00FFFF 10 32 32768 65536 98303 010000 017FFF 11 32 32768 98304 131071 018000 01FFFF 12 32 32768 131072 163839 020000 027FFF 13 32 32768 163840 196607 028000 02FFFF 14 32 32768 196608 229375 030000 037FFF 15 32 32768 229376 262143 038000 03FFFF SECTOR 1 - is used for Manufacture specific data i.e. serial number etc. SECTORS 2-15 are used to hold the FPGA configuration information. To program a new FPGA configuration 1. Sectors 2-15 must be erased 2. a new bit file must be uploaded to Sectors 2-15

Note that SECTOR 1 must not be ERASED as this contains detailed data about the camera.

SECTOR ERASE

The following command is used to erase a sector.

SECTOR xx ERASE - 0x53 0xAE 0x05 0x04 0xAA 0xBB 0xCC 0x00 0x50

Where the Hex Number AABBCC represents an address in the sector to be erased. After the

SECTOR erase command has been issued a small delay is required for the ERASE to take place.

Successful erase can be determined by polling the sector with the following command.

0x53 0xAF 0x01 0x50

If a value of 0xFF is returned the sector erase is complete.

Example Sector ERASEs

SECTOR 2 ERASE - 0x53 0xAE 0x05 0x04 0x00 0x10 0x00 0x00 0x50

0x53 0xAF 0x01 0x50 (Continue to poll until 0xFF received)



























SECTOR PROGRAMMING

Bursts of 32 DATA bytes (sixteen 16bit words) should be sent to the EPROM using a single

command, the EPROM will auto increment the addresses.

Burst write command

0x53 0xAE 0x25 0x02 0xAA 0xBB 0xCC 0xN1 0xN2 0xN3 ............0xN32 0x00 0x50

The address of the burst write is given by AABBCC, 32 DATA bytes as read from bit file are sent

N1-N32

Address AABBCC should start at the base address of sector 2 i.e. 0x001000 and increment by 16

for every burst command until the end of file.

At the end of file the last burst may not require 32bytes due to the file size, if this is the case the

last 32 should be padded out to 32. Data in padding ignored.

Notes :

- It is recommended to operate the camera with Command Ack. Waiting for a command Ack will

ensure burst writes have taken place before moving to the next burst write.

- The bit stream contains a check sum that is used by the FPGA during power up. If data is

corrupted during upload the FPGA will not boot.

- Verification that FPGA has successfully booted can be done by reading the FPGA version

number.

Example command list

Command TX bytes (to camera)

RX’d

bytes

(from

camera)

Comments

Enable FPGA

programming 0x4F 0x53 0x50 0x50

Enable cmd ack, Enable chk sum,

Hold FPGA in reset, enable

EPROM comms

Erase EEPROM

sector 2

0x53 0xAE 0x05 0x04 0x00

0x10 0x00 0x00 0x50 0x50

Confirm Sector 2

erase (by reading

LSByte)

0x53 0xAF 0x01 0x50 0xFF

0x50 Poll until 0xFF is returned

Erase EEPROM

sectors 3-15 and

confirm erase after

each sector.

As above with relevant sector

address As above

Poll after each sector is erased

until 0xFF is returned

Burst write 32

bytes of bit file

0x53 0xAE 0x25 0x02 0x00

0x10 0x00 0xN1 0xN2 0xN3

............0xN32 0x00 0x50

0x50 1st burst starting at Sector 2

address.

Multiple burst

writes of 32 bytes

of bit file

0x53 0xAE 0x25 0x02 0xAA

0xBB 0xCC 0xN1 0xN2 0xN3

............0xN32 0x00 0x50

0x50

Address 0xAABBCC starts at

sector 2 base address and needs to

be incremented by 16 for each

successive burst until end of file.

Enable External

Comms 0x4f 0x02 0x50 0x50

FPGA will now boot with new

firmware, need to delay approx.

500msec

Get FPGA version

0x53 0xE0 0x01 0x7E 0x50 0x50

Version 1.13

0x53 0xE1 0x01 0x50 0x01

0x50

0x53 0xE0 0x01 0x7F 0x50 0x50

0x53 0xE1 0x01 0x50 0x0D

0x50

Disable External

Comms 0x4F 0x52 0x50 0x50 Disable External Comms

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