Keysight 1GG6-4208 DC to 30 GHz Differential FET Limiting ... · – Lead pitch: 0.40 mm (0.016 in)...

Keysight 1GG6-4208 DC to 30 GHzDifferential FET Limiting Amplifier QFN

Data Sheet

Features – Two stage differential FET

traveling wave amplifier – Bandwidth DC to 30 GHz – Single-ended or differential

operation – Variable output power – Differential output power

@ 22 GHz: typ 15 dBm – AM noise @ 100 kHz, 3 GHz

carrier: typ –160 dBc @ max differential input power

– RoHS compliant and compatible

02 | Keysight | 1GG6-4208 DC to 30 GHz Differential FET Limiting Amplifier QFN - Data Sheet

DC specifications/physical properties1,2

Symbol Parameter/condition Min Typ Max Units

IG1 Gate1 current per stage –15 mA

IG2 Gate2 current per stage –10 uA

RinA, RinB Input resistance, each single ended input 45 50 55 Ohms

RoutA, RoutB Output resistance, each single ended output 45 50 55 Ohms

1. Ta = 25ºC, in and out ac coupled, VG1 = –13 V, VG2 = -3.25 V, VSS = –11.25V (Stage 1 and 2) unless otherwise specified

2. DC specifications for 1GG6-4208 die. Package performance may have moderate variance.

Absolute maximum ratings1

Symbol Parameter/condition Min Max Units

VG1A, VG1B Gate1 bias, Stage1 and Stage2 –13.5 0 Volts

VG2A, VG2B Gate2 bias, Stage1 and Stage2 –3.5 0 Volts

VSS1, VSS2 Source voltage, Stage1 and Stage2 –12 0 Volts

ISS1 Source current, Stage1 for chip in QFN package –80 0 mA

ISS2 Source current, Stage2 for chip in QFN package –70 0 mA

Pin, SE Maximum CW input power, single ended 19 dBm

Pin, DIFF Maximum CW input power, differential 22 dBm

Pdc pkg Power dissipation in QFN package 1.6 W

Tj Maximum junction temperature +150 ºC

Tbs2 Backside temperature +90 °C

Tstg Storage temperature –65 °C

Tmax Assembly temperature, (60 seconds maximum) 300 °C

1. Operation in excess of any of the values may result in permanent damage to the device.2. Tbs = 90ºC corresponds to 80ºC thermocouple measurement adjacent to QFN package on topside of

PCB with Pdc = 1.6 W. Note that a lower Tbs may be required due to PCB material, DC feedthrus or die attach epoxy limitations.

Properties – Package type: Quad flat -no

leads (SMT QFN) – Package dimensions:

3.0 x 3.0 mm (0.118 x 0.118 in) – Package thickness: 0.85

±0.10 mm (0.035 ±0.0039 in) – Lead pitch: 0.40 mm

(0.016 in) – Lead width: 0.20 mm

(0.008 in)

Description

The 1GG6-4208 is a differential two-stage traveling wave limiting amplifier. The output power can be adjusted with ISS current bias of the output stage. Operation can be single ended or differential. The 1GG6-4208 is fabricated using Keysight Technologies, Inc. GaAs pHEMT process which provides excellent process uniformity, reliability and high performance.


Frequency-domain AC specifications1,2


P6_100 Diff Pout @ Diff Pin=10 dBm, 6 GHz 12 16.5 25 dBm



DELTA6_100_50 Output power ratio, ISS2 = 50 to 100 mA @ Diff Pin = 10 dBm, 6 GHz 2 5.2 8 dB


DELTA12_100_50 Output power ratio, ISS2 = 50 to 100 mA @ Diff Pin = 10 dBm, 12 GHz 1.5 3.9 7 dB


DELTA22_100_50 Output power ratio, ISS2 = 50 to 100 mA @ Diff Pin = 10 dBm, 22 GHz 1 3.3 6.5 dB


Sdd11_6 Differential S11, 6 GHz –16 –12 dB





Sdd21_6 Differential S21, 6 GHz 7 11 dB

Sdd21_12 Differential S21, 12 GHz 6.5 10 dB



Sdd21_28 Differential S21, 28 GHz 5.5 10 dB











Noise_100 kHz3 AM noise @ 100 kHz offset, 3 GHz carrier, Diff Pin= 17 dBm –160 dBc

1. Ta = 25ºC, in and out ac coupled, VG1 = –13V, VG2 = –3.25 V, ISS = 100 mA (Stage 1 and 2) unless otherwise specified2. AC specifications for 1GG6-4208 die. Package performance may have moderate variance.3. Not measured: met by design.


ESD sensitivity1

Pad Parameter/condition Max Units

VG1A_1, VG1B_1, VG1A_2, VG1B_2 HBM2 400 V

VG2A_1, VG2B_1, VG2A_2, VG2B_2 HBM2 300 V

VSSA_, VSSB_1, VSSA_2, VSSB_2 HBM2 500 V

RFINA, RFINB HBM2 1500 V

RFOUTA, RFOUTB HBM2 1500 V

All QFN package pins CDM3 > 500 V

1. Tbs = 25°C, un-biased. Maximum limits are the first failure levels recorded during both ± polarity testing.2. Human body model: 100 pF, 1.5 kΩ. 3. Charge Device Model.

ESD Handling Precautions

III-V MMICs are ESD sensitive. Damage from ESD events can significantly affect III-IV MMIC performance and reliability. Preventative ESD measures must be employed in all aspects of storage, handling, and assembly, in compliance with the Keysight Technologies, Inc. ESD Control Program. Information on the Keysight ESD Control Program can be found at:

http://emg.communications.keysight.com/quality/esd/

For information on ESD precautions during die attach and bonding, please refer to Keysight Technologies GaAs MMIC ESD, Die Attach and Bonding Guidelines - Application Note, literature number 5991-3484EN.

Recommended Biasing1


VG1A, VG1B Gate1 bias, Stage1 and Stage1 –13 V

VG2A, VG2B Gate2 bias, Stage1 and Stage2 –3.25 V

ISS1 Stage1 Source Current –80 –75 mA

ISS2 Stage2 Source Current, chip in QFN packageOutput power control

–70 –65 mA

Nominal Bias

BiasingVG1 and VG2 and VSS (or ISS) are required for both Stage1 and Stage2 amplifiers. ISS or VSS can be used for output power control. Figures 10 and 11 show the typical relationship between VSS and ISS.

Bias sequenceTo power up VG2 biases must be applied first, followed by VG1 and then VSS (or ISS). Power down is the reverse.

There will be excess gate current if this sequence is not followed.

1. Long-term reliability is not guaranteed for device operation exceeding the min/max bias limits


Applications

The 1GG6-4208 is suitable for LO amplification or any application requiring a low-noise 30 GHz limiting amplifier. It can be operated with fixed bias or the output power can be adjusted with the second stage source current ISS2. With the variable output power feature the 1GG6-4208 can be used in ALC loops providing variable output power and gain.

RoHS Compliance

This device is RoHS Compliant. This means the component meets the requirements of the European Parliament and the Council of the European Union Restriction of Hazardous Substances Directive 2011/65/EU, commonly known as RoHS. The six regulated substances are lead, mercury, cadmium, chromium VI (hexavalent), polybrominated biphenyls (PBB) and polybrominated biphenyl ethers (PBDE). RoHS compliance implies that any residual concentration of these substances is below the RoHS Directive’s maximum concentration values (MVC); being less than 1000 ppm by weight for all substances except for cadmium which is less than 100 ppm by weight.

Moisture Compatibility

Injection mold components like the 1GG6-4208 in QFN are moisture-sensitive. The product is tested to the Moisture and Reflow Sensitivity Level 3 as per IPC/Jedec J-STD-020 and must be mounted within 168 hours of opening the shipping container. Store and handle parts for reflow and for rework per IPC/Jedec J-STD-033B. An example of the moisture sensitivity label is shown Figure 1.

Figure 1. MSL Label

Tape and Reel

The 1GG6-4208 is available in tape and reel format to facilitate automatic pick and place manufacturing. See Figure 13.


Figure 2. 1GG6-4208 block diagram

Figure 3. 1GG6-4208 Stage1 TWA simplified schematic diagram

50

50

50

50

RFINA

RFINB

RFOUTA

RFOUTB

TWAStage1

TWAStage2

VG 1_1 VG 2_1

VG 1_2 VG 2_2

VSS _1 VSS _2

VG 2A_1

VG 1A_1

VG 2B_1

VG 1B_1

VSS _1

VOUTAto stage2

VOUTBto stage2

RFINA RFINB

50 50

50 50


Figure 4. 1GG6-4208 QFN pin out diagram

GND

GND

GND

GND

GND

GND

RF_OUTA

RF_OUTB

RF_INA

RF_INB

GND

GND

16

17

181

2

3

11109

15

14

13

12

4

5

6

7 8

202122 1924 23V

G1A

_1

VG

2A_1

VS

SA

_1

VG

1A_2

VG

2A_2

VS

SA

_2

VG

1B_1

VG

2B_1

VS

SB

_1

VG

1B_2

VG

2B_2

VS

SB

_2

Figure 5. 1GG6-4208 QFN footprint diagram

This footprint is optimized for 10 mil Rogers 4350 layer 1 - 2 microstrip with a width of 20 mils.

Vias must be filled and plated over VIPPO recom-mend 7.9 mil FHS (no solder mask)

Use grounded 'area filled' copper on opposite side of board for proper heatsinking.

Use ‘area fill’ copper (grounded if possible) on inner layers for additional heatsinking

Add additional ground vias around the part where possible for additional heatsinking.

For footprints compatible with outer layout tools, please email [email protected]


Typical Performance1, 2

Figure 6. Typical differential S21, on eval board Figure 7. Typical differential S12, on eval board

5 10 15 20 250 30

2

4

6

8

10

12

0

14

Freq, GHz

dB(S

(2,1

))

1GG6-4208 on eval board - differential Sdd(2,1)

5 10 15 20 250 30

-90

-80

-70

-60

-50

-40

-30

-20

-10

-100

0

Freq, GHz

dB(S

(1,2

))

1GG6-4208 on eval board - differential Sdd(1,2)

Figure 8. Typical differential S11 and S22, on eval board

Figure 9. 1GG6-4208 eval board setup

5 10 15 20 250 30

-35

-30

-25

-20

-15

-10

-5

-40

0

Freq, GHz

dB(S

(1,1

))dB

(S(2

,2))

1GG6-4208 on eval board - eifferential Sdd(1,1) and Sdd(2,2)

1. Typical measurements of 1GG6-4208 QFN part taken on eval. board, including loss and mismatch of eval. board2. All measurements taken @ Ta=25ºC, ISS1= -80 mA, ISS2 = -70 mA, VG1 = -13 V, VG2 = -3.25 V, unless otherwise

noted. Please see Recommended Biasing information on page 4 for more information


Typical Performance1, 2

Figure 10. Typical VSS1 vs ISS1, wafer test ISS2 varied from –5 mA to –100 mA Figure 11. Typical VSS2 vs ISS2, wafer test ISS2 varied from -5 mA to -100 mA

0123456789

101112

0 10 20 30 40 50 60 70 80 90 100

-VS

S1

(V)

-ISS1 (mA)

1GG6-4095 -VSS1 vs -ISS1, ISS2 = -100 mA

-VSS1

0123456789

101112

0 10 20 30 40 50 60 70 80 90 100

-VS

S2

(V)

-ISS2 (mA)

1GG6-4095 -VSS2 vs -ISS2, ISS1= -100 mA

-VSS2

1. IV characteristics for 1GG6-4095 die. Package performance should be similar. Do not exceed maximum limits outlined in Absolute maximum ratings table.

2. All measurements taken @ Ta=25ºC, ISS1 = ISS2 = -100 mA, VG1 =-13 V, VG2 = -3.25 V, unless otherwise noted.Please see Recommended Biasing information on page 4 for more information


Figure 12. 1GG6-4208 dimension drawing

3.00 ±0.10

Pin 1

3

2

1

(0.02 typ)

(0.02 typ)

(0.15 typ)(0.40 typ)

Pin 24

(2.07)

(3X R0.10)

(R typ)-0.00

0.15

(0.18 typ)

XXXXXXXXYYWW

Pin 1

(0.29 typ)

(2.07)

Pin 24

3.00 ±0.10

Figure 13. 1GG6-4208 QFN tape and reel information

0.30

1.10

R0.300.10

4.00

2.00 ±0.05

8.00

3

1

3.30

AR 0.25

Ø1.50+0.10 0

Ø1.50 min

5.50 ±0.05

12.00 ±0.30

1.75 ±0.10

Notes: (Unless otherwise specified)1 10 sprocket hole pitch cumulative tolerance ±0.22. Camber in compliance with EIA 4813 Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole

3

Reel

Tape

User feeddirection Cover tape

Section A-Ascale 10 X

3.30


For more information on Keysight Technologies’ products, applications or services, please contact your local Keysight office. The complete list is available at:www.keysight.com/find/contactus

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DEKRA CertifiedISO9001 Quality Management System

www.keysight.com/go/qualityKeysight Technologies, Inc.DEKRA Certified ISO 9001:2015Quality Management System

This information is subject to change without notice.© Keysight Technologies, 2017Published in USA, April 5, 20175992-2189ENwww.keysight.com

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This data sheet contains a variety of typical and guaranteed performance data. The information supplied should not be interpreted as a complete list of circuit specifications. Customers considering the use of this, or other Keysight Technologies GaAs ICs, for their design should obtain the current production specifications from Keysight. In this data sheet the term typical refers to the 50th percentile performance. For additional information contact Keysight at [email protected].

The product described in this data sheet is RoHS Compliant. See RoHS Compliance section for more details.

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Keysight 1GG6-4208 DC to 30 GHz Differential FET Limiting ... · – Lead pitch: 0.40 mm (0.016 in)...

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