Key Success Factor of SSDKey Success Factor of SSD

Hynix Semiconductor Inc.

Oct. 20, 2008

2

Presentation Agenda

-- Raw NANDRaw NAND-- Performance & ReliabilityPerformance & Reliability

Key Success FactorKey Success Factor

Market IntroductionMarket Introduction

ConclusionConclusion

3

0.4 0.9 2.24.5

6.5

10.6 11.514.5

15.918.2

21.424.1

13%18%15%10%

26%

8%

63%

44%

105%

144%125%

0

10

20

30

40

2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 20110

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

Revenue Growth

CAGR: 15% (2008~2011)

Unit : B$

Source : WSTS

Slower but Continuous Growth in NAND Market from 2008

NAND Market Forecast: OverallNAND Market Forecast: Overall

4

Strong & Continuous Demand from PC Storage

Source : Hynix Marketing

Unit : Mpcs (8Gb EQ)

0 10,000 20,000 30,000 40,000 50,000 60,000 70,000

'12

'11

'10

'09

'08

'07

Game

Mobile Phone DSCUSBMP3 /PMPPC StorageOthers

432% 111% 84% 83% 114% 61%

25%

3%

PCStorage

5%

6%

Others

9%

13%

USB

27%

25%

MobilePhone

8%

17%

DSC

2%24%2012

2%34%2008

GameMP3/PMPPortion

4,047

1,785

8,610

18,250

33,385

58,850

NAND Application TrendNAND Application Trend

5

0

10

20

30

40

50

60

70

2008 2009 2010 2011 20120

40

80

120

160

200

240

280Shipment Avg. GB

PC will be a new killer application of NAND

Source : Hynix Marketing

10%

19%

24%

25%

PC Portion in NAND Market SSD Market ForecastUnit : Mpcs Unit : GB

2.6%

SSD Market ForecastSSD Market Forecast

0

10000

20000

30000

40000

50000

60000

70000

2008 2009 2010 2011 2012

70

60

50

40

30

20

10

0

Unit : Bpcs (8Gb EQ)

6

Source : Hynix Marketing

0.3%

0.8%

1.5%

2.0%

0

50

100

150

200

2009 2010 2011 2012

0%

1%

1%

2%

2%

3%

DT DT with SSD Portion

[Desktop]

13%

21%

25%

6%

0

50

100

150

200

250

2009 2010 2011 2012

0%

5%

10%

15%

20%

25%

30%

NB NB with SSD Portion

[Notebook]

6%

13%

27%

3%

0

2

4

6

8

10

12

2009 2010 2011 2012

0%

5%

10%

15%

20%

25%

30%

Server Server with SSD Portion

[Server]Unit : Mpcs

SSD Adoption Rate in Computing DeviceSSD Adoption Rate in Computing Device

7

Server

Notebook

Enterprise

UMPC

MID

Low-cost PC

GPS Navigation

DVC

Computing Device

ConsumerDevice

[HDD Type]

[Module Type]

[Chip Type]

I/F: SATA 3Gbps

Size: 1.8”, 2.5”

Density: 256GB in 2009

I/F: PATA, SATA

Size: Customized

Density: 64GB in 2009

I/F: eMMC

Size: 14 x 18 x 1.3 mm, 169FBGA

Density: 32GB in 2009

SSD Market SegmentationSSD Market Segmentation

8

Presentation Agenda

-- Raw NANDRaw NAND-- Performance & ReliabilityPerformance & Reliability

Key Success FactorKey Success Factor

Market IntroductionMarket Introduction

ConclusionConclusion

9

19MB/sec

112MB/sec

HS-NAND

(MLC)

16MB/sec

38MB/sec

Standard NAND

(MLC)

Write Performance

Read Performance

2Plane with Interleave + 2CE

38MB/sec

2Plane with Interleave + 2CE

38MB/sec

RemarkStandard NAND

(SLC)

NAND Performance Comparison

Standard NAND: tPROG=200us(SLC)/800us(MLC), tRC/tWC=25ns, tR=25us(SLC)/50us(MLC)

HS-NAND : tPROG=800us(MLC), tRC/tWC=7.5ns, tR=50us

Standard NAND

HS-NAND

Command,Address,Data for page0

Command,Address,Data for page1

Command,Address,Data for page2

900us300us 600us 1200us 1500us 1800us 2100us

tPROG=800us

tPROG=800us

tPROG=800us

tPROG=800us

100us 100us 100us

30us 30us 30us tPROG=800us

10

Interface SpeedCycle time(tRC/tWC) is important for NAND performance

Maximize the performance using by high speed interface scheme

HS-NAND (High speed NAND, DDR)

Comparison between HS NAND and STD NAND

2.7V ~ 3.6VVCC2.7V ~ 3.6V

YesScalable Higher PerformanceNo

YesCache ModeSome

1.7V ~ 1.95VVCCq2.7V ~ 3.6V

7.5ns (DDR)tRC/tWC≥ 25ns (SDR)

YesSynchronous InterfaceNo

HS-NAND

(ONFI 2.0)

Standard NAND

(ONFI 1.0)Feature

11

Migration for NAND Cell structure

0%

25%

50%

75%

100%

2007 2008 2009 2010

Now4Q ‘08

Source : Hynix Marketing

SSD : <64GBSLC 2GB

128GBMLC 8GB

256GB16GB

512GB16GB

Floating Gate 5XnmFloating Gate 5Xnm

F.G 4XnmF.G 4Xnm

F.G or CTD

CTD will be one of solution for <3xnm NAND

12

Characteristics of CTD Technology

Floating gate spacing limitation; ~35nm

Cell to cell interference

Retention

CTD (Charge Trap Device)

What are the critical issues?

13

Introduction to CTD

Floating Gate Cell

F. Gate

C. Gate

Tunnel Oxide

Nitride

C. Gate

Tunnel Oxide

Blocking Oxide

S D

S D

CTD Cell(TANOS/SONOS)

Thermal Oxide

Poly-silicon

(Free Electron)

Top Oxide/Nitride

/ Bottom Oxide

Poly-silicon

Tunnel

Oxide

Floating Gate

IPD

(ONO)

Control Gate

Thermal Oxide

Nitride

(Trapped electron)

High-K Dielectric

Metal Gate

Tunnel

Oxide

Charge Trap

Blocking Oxide

Control Gate

Structure & X-section Material

IPD

14

Electrical Characteristics of CTD

Better E/W Characteristics

Less Interference

E/W Cycling Characteristics Cell-to-Cell Interference

than FG NAND

15

Advantages of CTD

CTD will drive Flash-SSD technology

16

Presentation Agenda

-- Raw NANDRaw NAND-- Performance & ReliabilityPerformance & Reliability

Key Success FactorKey Success Factor

Market IntroductionMarket Introduction

ConclusionConclusion

17

Factors to enhance NAND performance - I

Maximize NANDPerformance

Large Page(4KB/8KB)

Optimize AC Timings

Optimize BUS Activities

Cache Program/Read

Multi-PlaneOperation

InterleavedOperations

Performance can be enhanced by key parameters(Multi chip operation, Larger page device, Cache Program/Read, etc)

18

How to enhance the NAND performance ?

-Multi-channel, Multi-way interleaving parallelism.

26.4

78.4

13.2

39.2

6.6

19.6

1PLANE 2WAY

MLC

MLC

MLC

SLC

SLC

SLC

119.2108.494.853.247.63023.614.813.2

59.654.247.426.623.81511.87.46.6

29.827.123.713.311.97.55.93.73.3

119.2

59.6

29.8

1PLANE 8WAY

119.2114113.6113.6112.458.459.639.24

59.65756.856.856.229.229.819.62

29.828.528.428.428.114.614.99.81

2PLANE 8WAY

2PLANE 4WAY

1PLANE 4WAY

2PLANE 2WAY

2PLANE CACHE

2PLANECACHE1PLANECHANNEL

SLC PAGE SIZE : 4K, tWC : 25ns, tPROG : 200us

MLC PAGE SIZE : 4K, tWC : 25ns, tPROG : 800usUNIT [MB/S]

Factors to enhance NAND performance - II

19

Performance Data

SLC- Page Size : 4KB- tWC : 25ns- tPROG : 200us

MLC- Page Size : 4KB- tWC : 25ns- tPROG : 800us

MB/S MB/S

20

E/W endurance is related with tech and type of cell.Tech. shrink cause to lower E/W performance, so optimal wear-leveling must be required.

Introduction of Wear-leveling - I

21

Dynamic Wear LevelStatic Wear LevelGlobal Wear Level

BLOCK

1

BLOCK

2

BLOCK

3

BLOCK

4

BLOCK

5

BLOCK

6

BLOCK N

-

2

BLOCK N

-

1

BLOCK N

Write Access

Compare E/W Cycle

OCCU

PIED

FREE OR

BUFFER

Victim Block

Does not need additional copy back

Does not need additional block erase

Introduction of Wear-leveling - II

22

Dynamic Wear LevelStatic Wear LevelGlobal Wear Level

BLOCK

1

BLOCK

2

BLOCK

3

BLOCK

4

BLOCK

5

BLOCK

6

BLOCK N

-

2

BLOCK N

-

1

BLOCK N

Static Wear Level

Source Block

Compare E/W Cycle

OCCU

PIED

FREE OR

BUFFER

Victim Block

Need additional copy back

Need additional block erase

Introduction of Wear-leveling - III

23

Dynamic Wear LevelStatic Wear LevelGlobal Wear Level

Introduction of Wear-leveling -Ⅳ

CHIP 0

BLO

CK

Nth

Global Wear Level

Target Block

Victim BlockCompare E/W Cycle between Chips

CHIP N

BLOCK M

th

Every global wear level cause

Additional copy back

Additional block erase

24

Performance trade-off by Wear-leveling

Frequent wear leveling may degrade performance

Additional E/W cycle + Read out & Write back

Wear level threshold

25

Advanced Controller (Hardwired-FTL)

Command Data Transfer

Latency Factors• Address transition• Map table Look-up• Define write buffer policy; Random or Sequential• (Channel 1)• Data transfer• (Channel 2)• Data transfer• (Channel 3)• …

Software based FTL causes Long latency

Reduced by Hardwired FTL

26

Presentation Agenda

-- Raw NANDRaw NAND-- Performance & ReliabilityPerformance & Reliability

Key Success FactorKey Success Factor

Market IntroductionMarket Introduction

ConclusionConclusion

27

Conclusion

• Limitation of current FG technology should beresolved by adopting new technology(CTD)

• High Speed interface enhances the performance

• Optimal Wear-leveling algorithm satisfying bothPerformance and Reliability

• Complexities of NAND Management require Hard-wired FTL design

Thank You !!!