Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University State & Finite State Machines...
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![Page 1: Kevin Walsh CS 3410, Spring 2010 Computer Science Cornell University State & Finite State Machines See: P&H Appendix C.7. C.8, C.10, C.11.](https://reader036.fdocuments.in/reader036/viewer/2022062516/56649d2d5503460f94a03dd9/html5/thumbnails/1.jpg)
Kevin WalshCS 3410, Spring 2010
Computer ScienceCornell University
State & Finite State Machines
See: P&H Appendix C.7. C.8, C.10, C.11
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Prelim 1: 3/18/2010 (evening)Prelim 2: 4/27/2010 (evening)
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Unstable Devices
B
A
C
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Bistable Devices
Stable and unstable equilibria?
B
A
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Summary
So far:• Current output depends only on current input
(no internal state)
Need a way to record data• … a way to build stateful circuits• … a state-holding device
Inputs Combinationalcircuit
OutputsN M
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SR Latch
Set-Reset (SR) LatchStores a value Q and its complement Q
S R Q Q
0 0
0 1
1 0
1 1
S
R
Q
Q
S
R
Q
Q
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Unclocked D Latch
Data (D) Latch
D Q Q
0
1
S
R
D Q
Q
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D Latch with Clock
S
R
D
clk
Q
Q
clk
DQ
Level Sensitive D LatchClock high: set/reset (according to D)Clock low: keep state (ignore D)
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Clocks
Clock helps coordinate state changes• Usually generated by an oscillating crystal• Fixed period; frequency = 1/period
1
0
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Edge-Triggered D Flip-Flop
D Flip-Flop• Edge-Triggered• Data is captured
when clock is high• Outputs change only
on falling edges
D Q
Q
D Q
Qc
FL L
clk
D
F
Q
c
Q
Q
D
clk
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Clock Disciplines
Level sensitive• State changes when clock is high (or low)
Edge triggered• State changes at clock edge
positive edge-triggered
negative edge-triggered
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Registers
Register• D flip-flops in parallel • shared clock• extra clocked inputs:
write_enable, reset, …
clk
D0
D3
D1
D2
4 44-bitreg
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Metastability and Asynchronous Inputs
1-bitreg
Clk
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Metastability and Asynchronous Inputs
Q: What happens if input is changes near clock edge?
A: Google “Buridan’s Principle” by Leslie Lamport
1-bitreg
Clk
01
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An Example
32-bitreg
Clk
+1
Run
WE R
Reset
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Clock Methodology
Clock Methodology• Negative edge, synchronous
– Signals must be stable near falling clock edge
• Positive edge synchronous• Asynchronous, multiple clocks, . . .
clk
compute save
tsetup thold
compute save compute
tcombinational
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Voting Machine
mux
32
...reg
dete
ct
enc
3
decoder (3-to-8)
32 32
32
LED
dec
3
WE
+1
regWE
regWE
regWE
mux
D
V
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Automata Model
Finite State Machine
• inputs from external world• outputs to external world• internal state• combinational logic
Next State
Current State
Input
Output
Regi
ster
s
Comb.Logic
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FSM Example
Legend
state
input/output
startstate
A B
C D
down/onup/off down/on
down/off
up/off
down/off
up/offup/off
Input: up or downOutput: on or offStates: A, B, C, or D
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FSM Example Details
Legend
S1S0
i0i1i2…/o0o1o2…
S1S0
00 01
10 11
1/10/0 1/1
1/0
0/0
1/0
0/00/0
Input: 0=up or 1=downOutput: 1=on or 1=offStates: 00=A, 01=B, 10=C, or 11=D
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General Case: Mealy Machine
Outputs and next state depend on bothcurrent state and input
Mealy Machine
Next State
Current State
Input
OutputRe
gist
ers
Comb.Logic
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Moore Machine
Special Case: Moore Machine
Outputs depend only on current state
Next State
Current State
Input
OutputRe
gist
ers Comb.Logic
Comb.Logic
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Moore Machine Example
Legend
stateout
input
startout
A off
Bon
C off
D on
downup down
down
up
down
upup
Input: up or downOutput: on or offStates: A, B, C, or D
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Digital Door Lock
Digital Door LockInputs: • keycodes from keypad• clockOutputs: • “unlock” signal• display how many keys pressed so far
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Door Lock: Inputs
Assumptions:• signals are synchronized to clock• Password is B-A-B
KAB
K A B Meaning0 0 0 Ø (no key)1 1 0 ‘A’ pressed1 0 1 ‘B’ pressed
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Door Lock: Outputs
Assumptions:• High pulse on U unlocks door
UD3D2D1D0
4 LEDdec
8
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Door Lock: Simplified State Diagram
Idle
G1
”0”
Ø
G2 G3
B1 B2
”1” ”2” ”3”, U
”1” ”2”
Ø Ø
Ø Ø
“B”
“A” “B”
else
else
any
anyelse else
B3”3”
else
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Door Lock: Simplified State Diagram
Idle
G1
”0”
Ø
G2 G3
B1 B2
”1” ”2” ”3”, U
”1” ”2”
Ø Ø
Ø Ø
“B”
“A” “B”
else
else
else
anyelse else
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Door Lock: Simplified State Diagram
Idle
G1
”0”
Ø
G2 G3
B1 B2
”1” ”2” ”3”, U
”1” ”2”
Ø Ø
Ø Ø
“B”
“A” “B”
else
else
else
anyelse else Cur. State OutputCur. State OutputIdle “0”G1 “1”G2 “2”G3 “3”, UB1 “1”B2 “2”
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Door Lock: Simplified State Diagram
Idle
G1
”0”
Ø
G2 G3
B1 B2
”1” ”2” ”3”, U
”1” ”2”
Ø Ø
Ø Ø
“B”
“A” “B”
else
else
else
anyelse else
Cur. State Input Next StateCur. State Input Next StateIdle Ø IdleIdle “B” G1Idle “A” B1G1 Ø G1G1 “A” G2G1 “B” B2G2 Ø B2G2 “B” G3G2 “A” IdleG3 any IdleB1 Ø B1B1 K B2B2 Ø B2B2 K Idle
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Cur. State Input Next StateIdle Ø IdleIdle “B” G1Idle “A” B1G1 Ø G1G1 “A” G2G1 “B” B2G2 Ø B2G2 “B” G3G2 “A” IdleG3 any IdleB1 Ø B1B1 K B2B2 Ø B2B2 K Idle
State Table Encoding
Cur. State OutputIdle “0”G1 “1”G2 “2”G3 “3”, UB1 “1”B2 “2”
UD3D2D1D0
4dec
8
D3 D2 D1 D0 U0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 10 0 0 1 00 0 1 0 0
RPQ
K A B Meaning0 0 0 Ø (no key)1 1 0 ‘A’ pressed1 0 1 ‘B’ pressed
K A B0 0 01 0 11 1 00 0 01 1 00 0 10 0 00 0 10 1 0x x x0 0 01 x x0 0 01 x x
S2 S1 S0
0 0 00 0 10 1 00 1 11 0 01 0 1
State S2 S1 S0
Idle 0 0 0G1 0 0 1G2 0 1 0G3 0 1 1B1 1 0 0B2 1 0 1
S2 S1 S0 S’2 S’1 S’0
0 0 0 0 0 00 0 0 0 0 10 0 0 0 0 10 0 1 0 0 10 0 1 0 1 00 0 1 0 1 00 1 0 0 1 00 1 0 0 1 10 1 0 0 0 00 1 1 0 0 01 0 0 1 0 01 0 0 1 0 11 0 1 1 0 11 0 1 0 0 0
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Door Lock: Implementation
4
dec
3bitReg
clk
UD3-0S2-0
S’2-0
S2-0
AB
C
Strategy:(1) Draw a state diagram (e.g. Moore Machine)(2) Write output and next-state tables(3) Encode states, inputs, and outputs as bits(4) Determine logic equations for next state and outputs
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Summary
We can now build interesting devices with sensors• Using combinational logic
We can also store data values• Stateful circuit elements (D Flip Flops, Registers, …)• Clock to synchronize state changes• But be wary of asynchronous (un-clocked) inputs• State Machines or Ad-Hoc Circuits