k Input, m Output Lookup Tables - sportlab.usc.edusportlab.usc.edu/~msaeedi/slides/DATE_2013.pdf ·...
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Reversible Logic Synthesis ofk‐Input, m‐Output Lookup Tables
Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
University of Southern California
Department of Electrical Engineering
Supported by the IARPA Quantum Computer Science
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• Introduction
• Lookup Tables (LUT)
– Quantum Walk on Binary Welded Tree
• Related Work
• Proposed Synthesis Algorithm
• Simulation Results
• Conclusion
Outline
17‐Mar‐13 1Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
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• Data is carried out by quantum bits or qubits
• Quantum gates
– Unitary matrix ( )– Reversible
• Multiple‐Control Toffoli (MCT) gate
– Negative Control
– Positive Control
Quantum Circuits
17‐Mar‐13 2Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
x
y
z
w
x
y
z
wow’ if (x=0 & y=1 & z=1)w otherwise
Control lines remain unchanged
Target line
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• Quantum algorithms
– Quantum part, e.g., Quantum Fourier Transform
– Classical part, or Oracles
• Reversible synthesis methods
• General purpose vs. special purpose synthesis
• Automatic synthesis of a specific type of quantum circuits
– Quantum walk on binary welded tree
– Modular exponentiation circuits
Reversible Logic Synthesis
17‐Mar‐13 3Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
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• Random movement on a Binary Welded Tree (BWT)
• Oracle [1]:
Quantum Walk on Binary Welded Tree
17‐Mar‐13 4Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
Node a Node b
Color c
a b
7 16
8 17
9 15
11 19
12 22
13 18
14 20
For black edges[1] A. M. Childs et al., “Exponential algorithmic speedup by a quantum walk,” in Proc. of the 35th Annual ACM Symposium on Theory of Computing, pp. 59–68, 2003.
Vc(a) = b
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• Look‐Up Table (LUT)
– read‐only inputs
– zero‐initialized outputs
• LUT realization with MCT gates
– e.g., 16 7
LUT Synthesis
17‐Mar‐13 5Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
00
0
0
0
16 = (10000)2
7 = (00111)2
x0
x4
y0
y4
x y
16 7
x4x3x2x1x0 y4y3y2y1y0
10000 00111
00
0
0
0
x0
x4
y0
y4
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• Straightforward implement the oracle for black edges
– High cost
Oracle Implementation
17‐Mar‐13 6Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
7 16 16 7
a y
7 16
8 17
9 15
11 19
12 22
13 18
14 20
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• ESOP‐based methods [2]
– output, a minterm of
–– Use an ESOP minimizer to minimize
• General‐purpose reversible synthesis methods [3]
– Copying input registers into output registers
– Apply synthesis algorithm on output register
Related Work
17‐Mar‐13 7Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
[2] K. Fazel, M. Thornton, and J. Rice, “ESOP‐based Toffoli gate cascade generation,” in PACRIM, pp. 206 –209, Aug. 2007.[3] M. Saeedi and I. L. Markov, “Synthesis and optimization of reversible circuits ‐ a survey,” ACM Computing Surveys, arXiv:1110.2574, 2013.
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• Cube sharing [4]
– To reduce the number of MCT gates
• Cofactor sharing
– To reduce the number of control lines
• Un‐computation
– To reuse the ancilla line
• Look‐ahead search
– To improve the quality of results
Proposed Synthesis Algorithm
17‐Mar‐13 8Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
[4] N. M. Nayeem and J. E. Rice, “A shared‐cube approach to ESOP‐based synthesis of reversible logic,” in Facta universitatis ‐ series: Electronics and Energetics, vol. 24, no. 3, pp. 385–402, Dec. 2011.
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• Reduces the number of MCT gates
Cube Sharing
17‐Mar‐13 9Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
y0 = c1+abcy1 = abc
y0 = c1+abcy1 = c2+abc
No cube sharing Zero‐initialized ancilla available
c1+c2
c2+abc
c1+c2+c2+abc=c1+abc
+: modulo 2 addition
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• Reduces the number of control lines
Cofactor Sharing
17‐Mar‐13 10Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
y0 = aby1 = abc
ab is the shared cofactor, which is also a cube for y0
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• Ancilla reuse
Un‐computation
17‐Mar‐13 11Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
y0 = abcy1 = abd
ab is the shared cofactor, but does not appear on neither of the outputs
Zero‐initialized ancilla available Un‐computation of ab
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• 3‐input, 6‐output LUT
Example
17‐Mar‐13 12Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
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Example: Lists
17‐Mar‐13 13Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
cube_listinput to the synthesis algorithm
shared_cofactor_list
constructed by pair‐wise comparison of cubes
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• Pick a shared cofactor, implement it along with all its dependent cubes
• Which shared cofactor to choose first?
Synthesis
17‐Mar‐13 14Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
S1 S2 S3
C1 C2 C3 C4 C5 C6
S2 S3
C4 C5 C6
If we choose S1, then C1, C2, and C3 will be created
After removing S1, C1, C2, and C3, S2is no more a shared cofactor
Si: shared cofactors, Ci: cubes
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• Exhaustive search until depth d
• Find path p with the lowest cost
• Pick the first node (from top) in p as the shared cofactor
Look‐ahead Search
17‐Mar‐13 15Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
Level‐0 shared cofactors
Remaining shared cofactors at Level‐i
look‐ahead depth
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Synthesis Algorithm
17‐Mar‐13 16Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
look‐ahead search
synthesis
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• Implemented in C++
• EXORCISM‐4 [5] to initially construct a minimized ESOP representation
• At most one ancilla in all circuits
• 3‐level of look‐ahead (d = 3)
• Intel Core i7‐2600, 8GB memory
Simulation Setup
17‐Mar‐13 17Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
[5] A. Mishchenko and M. Perkowski, “Fast heuristic minimization of exclusive sum‐of‐products,” in Reed‐Muller Workshop, 2001.
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• 28% (on average ) improvement over [13]– Runtime from a few seconds to about 5 minutes
Results: MCNC Benchmarks
17‐Mar‐13 18Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
[13] N. M. Nayeem and J. E. Rice, “A shared‐cube approach to ESOP‐based synthesis of reversible logic,” in Facta universitatis ‐ series: Electronics and Energetics, vol. 24, no. 3, pp. 385–402, Dec. 2011.
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• 52% (on average ) improvement over [7, Table 8]– Runtime less than one minute in our method– (# of Toffoli, # of CNOT, cost)
Results: Modular Exponentiation (1)
17‐Mar‐13 19Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
[7] I. L. Markov and M. Saeedi, “Constant‐optimized quantum circuits for modular multiplication and exponentiation,” QIC., vol. 12, no. 5‐6, pp. 361–394, May 2012.
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Results: Modular Exponentiation (2)
17‐Mar‐13 20Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
[7] I. L. Markov and M. Saeedi, “Constant‐optimized quantum circuits for modular multiplication and exponentiation,” QIC., vol. 12, no. 5‐6, pp. 361–394, May 2012.
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• (4, 7)‐LUT in modular exponentiation for M = 65
Sample Circuit
17‐Mar‐13 21Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
Can be removed by a post‐synthesis optimization process
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• A synthesis algorithm for LUT’s by reversible gates
– Cofactor Sharing
– Un‐computation
– Look‐ahead Search
• Improvement of synthesis cost
– 52% on average in modular exponentiation algorithm
– 28% on average on the MCNC benchmarks
Conclusion
17‐Mar‐13 22Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
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17‐Mar‐13 23Alireza Shafaei, Mehdi Saeedi, Massoud Pedram
Department of Electrical Engineering, University of Southern California
Thank you!