Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.
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Transcript of Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.
![Page 1: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/1.jpg)
1
ON THE INTERACTION BETWEEN POWER-AWARE
FPGA CAD ALGORITHMS
Julien Lamoureux and Steven J.E Wilton
ICCAD 2003
![Page 2: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/2.jpg)
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Outline
Introduction
Algorithms
Experimental results
Conclusion
![Page 3: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/3.jpg)
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Introduction
Technology Mapping(CutMap)
Clustering(T-VPack)
Placement(VPR:T-VPlace)
Routing(VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
![Page 4: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/4.jpg)
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Introduction
Technology Mapping(CutMap)
Clustering(T-VPack)
Placement(VPR:T-VPlace)
Routing(VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
![Page 5: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/5.jpg)
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Introduction
AB
C
DE
mapping
f2
f3
f1AB
C
DEF
Technology mapping transforms a netlist of gates and registers into a netlist of K-input lookup tables (K-LUTs) and registers.
...
fSRAM
x
y
z...
001
0
...1
![Page 6: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/6.jpg)
6
Introduction
Technology Mapping(CutMap)
Clustering(T-VPack)
Placement(VPR:T-VPlace)
Routing(VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
![Page 7: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/7.jpg)
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Introduction
Technology Mapping(CutMap)
Clustering(T-VPack)
Placement(VPR:T-VPlace)
Routing(VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
![Page 8: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/8.jpg)
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Introduction Figure 1: An N cluster
Figure 2: A LUT and flip-flop BLE
![Page 9: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/9.jpg)
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Introduction
Technology Mapping(CutMap)
Clustering(T-VPack)
Placement(VPR:T-VPlace)
Routing(VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
![Page 10: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/10.jpg)
10
Introduction
Technology Mapping(CutMap)
Clustering(T-VPack)
Placement(VPR:T-VPlace)
Routing(VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
![Page 11: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/11.jpg)
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f3
f2
f1
Introduction
A
B
C
DEF
f1
f2 f3
ABC
DEF
Mapping + Clustering
PlacementRouting
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Algorithms
Technology Mapping(EMap)
Clustering(P-T-VPack)
Placement(P-T-VPlace)
Routing(P-VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
![Page 13: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/13.jpg)
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Algorithms
Technology Mapping(EMap)
Clustering(P-T-VPack)
Placement(P-T-VPlace)
Routing(P-VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
![Page 14: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/14.jpg)
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Technology Mapping
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Technology Mapping
![Page 16: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/16.jpg)
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Algorithms
Technology Mapping(EMap)
Clustering(P-T-VPack)
Placement(P-T-VPlace)
Routing(P-VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
![Page 17: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/17.jpg)
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Algorithms
Technology Mapping(EMap)
Clustering(P-T-VPack)
Placement(P-T-VPlace)
Routing(P-VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
![Page 18: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/18.jpg)
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Clustering
T-VPack
P-T-VPack
Crit(B) is a measure of how close LUT B is to being on the critical path, Nets(B) is the set of nets connected to LUT B, Nets(C) is the set of nets connected to the LUTs already selected for cluster C
Activity(i) is the estimated switching activity of net i, Activityavg is the average switching activity of all the nets in the user circuit.
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Clustering
![Page 20: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/20.jpg)
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Algorithms
Technology Mapping(EMap)
Clustering(P-T-VPack)
Placement(P-V-Place)
Routing(P-VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
![Page 21: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/21.jpg)
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Algorithms
Technology Mapping(EMap)
Clustering(P-T-VPack)
Placement(P-T-VPlace)
Routing(P-VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
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Placement
T-Vplace
P-T-VPlace
q(i) is used to scale the bounding boxes to better estimate wirelength for nets with more than 3 terminals, as described in
[9]. Delay(i,j) is the estimated delay of the connection from source i to sink j, CE is a
constant, and Criticality(i,j) is an indication of how close to the critical path the connection is [9]. bbx(i) and bby(i) are the x and y dimensions of the bounding
box of net i
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Placement
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Algorithms
Technology Mapping(EMap)
Clustering(P-T-VPack)
Placement(P-T-VPlace)
Routing(P-VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
![Page 25: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/25.jpg)
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Algorithms
Technology Mapping(EMap)
Clustering(P-T-VPack)
Placement(P-T-VPlace)
Routing(P-VPR Router)
Circuit
Delay / Area / Power Estimations
FPGA CAD FLOW
![Page 26: Julien Lamoureux and Steven J.E Wilton ICCAD 2003 1.](https://reader031.fdocuments.in/reader031/viewer/2022032607/56649eca5503460f94bd93e4/html5/thumbnails/26.jpg)
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Routing
VPR-Router
P-VPR-Router
The baseline VPR router uses the following cost function to evaluate a routing track n
while forming a connection from source i to sink j:
b(n) is the “base cost”, h(n) is the historical congestion cost, and p(n) is the present
congestion of node n.
Activity(i) is the switching activity in net i, MaxActivity is the maximum switching
activity of all the nets, and MaxActCrit is the maximum activity criticality that any net can have. cap(n) is the capacitance associated with routing resource node n and ActCrit(i) is the activity criticality of
net i.
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Routing
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Experimental results
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Node Duplication 3-LUTs mappings:
With duplication No duplication