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Application Note

PowerPCEmbedded Controller JTAG Reset Requirements

JTAGReset.fm

May 2002 Page 1

Scope

The PowerPC 405 and 440 series of embedded

controllers feature an IEEE 1149.1 JTAG TestAccess Port (TAP) for both debug and board-level

test use. For correct device operation, the JTAG

TAP controller must be reset at system power-on.

This application note provides several options for

resetting the TAP controller, while maintaining func-

tionality with JTAG-based debug tools such as the

IBM RISCWatch debugger.

JTAG TAP Reset Requirements

The IEEE Standard Test Access Port and

Boundary-Scan Architecture (IEEEStd 1149.1-

1990) specifies that the JTAG TAP controller must

be reset at power-up, either via a dedicated TRST

input signal, or through circuitry built into the test

logic. It is further required that the TAP controller

must not be initialized by any other chip I/O, such as

a system reset.

Since IBM PowerPC embedded controllers do not

include internal circuitry to detect a power-up condi-

tion and reset the TAP controller, TRST must be

asserted during power-on to reset the TAP

controller. Furthermore, TRST must not be directly

or logically connected to SysReset. Doing soviolates the requirement that the level on the

SysReset input must not reset the JTAG TAP

controller.

Resetting the JTAG TAP Controller

Designers can chose one of two methods to reset

the JTAG controller. The simplest implementation,

shown in Figure 1, holds the TAP controller in reset

unless a JTAG-based debugger is connected. Since

keeping the TAP controller in reset places all of the

chip I/Os in functional mode, this solution is the

simplest and easiest to implement. The only draw-back is that if a JTAG-based debugger is attached

during a power-on sequence, the debugger may

hold TRST high and prevent the TAP controller from

being reset.

The circuit depicted in Figure 2 provides a solution

that ensures the TAP controller resets in responseto either a power-on reset or assertion of TRST from

a JTAG-based debugger or a board-level boundary

scan tool. Observe that SysReset, which may be

actively driven by the PowerPC Embedded

Controller, does not affect the TRST input. This is

required as TRST must be not activated in response

to a system reset.

References

1. IEEE Standard Test Access Port and Boundary-

Scan Architecture. 1990. (IEEE Std 1149.1-

1990.)

Figure 1. Minimal TRST Wiring

Figure 2. Recommended TRST Wiring

TRST

POR

TRSTJTAG-basedDebugger

SysReset

PowerPC

EmbeddedController

1k

3.3k

Power OnReset

TRST

Power OnReset

POR

TRSTJTAG-basedDebugger

SysReset

PowerPC

EmbeddedController

1k

10k

3.3k

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Copyright and Disclaimer

Copyright International Business Machines Corporation 2002

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