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Journal of Science: Advanced Materials and Devices 2 (2017) 501e514

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Journal of Science: Advanced Materials and Devices

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Original Article

Fabrication, electrical characterization and device simulation ofvertical P3HT field-effect transistors

Bojian Xu a, b, c, Tamer Dogan a, Janine G.E. Wilbers a, 1, Michel P. de Jong a,Peter A. Bobbert a, d, *, Wilfred G. van der Wiel a, **

a NanoElectronics Group, MESAþ Institute for Nanotechnology, University of Twente, P.O. Box 217, 7500 AE Enschede, The Netherlandsb Shenzhen Guohua Optoelectronics Tech. Co. Ltd., Shenzhen 518110, Chinac SCNU-TUE Joint Lab of Device Integrated Responsive Materials (DIRM), National Center for International Research on Green Optoelectronics, South ChinaNormal University, No. 378, West Waihuan Road, Guangzhou Higher Education Mega Center, Guangzhou 510006, Chinad Molecular Materials and Nanosystems, Department of Applied Physics, Eindhoven University of Technology, P.O. Box 513, 5600 MB Eindhoven, TheNetherlands

a r t i c l e i n f o

Article history:Received 13 October 2017Received in revised form9 November 2017Accepted 11 November 2017Available online 20 November 2017

Keywords:Vertical organic field-effect transistor(VOFET)P3HT (poly[3-hexylthiophene-2,5-diyl])Wedging transferReactive ion etchingATLAS device simulation

* Corresponding author. NanoElectronics GrouNanotechnology, University of Twente, P.O. Box 2Netherlands.** Corresponding author.

E-mail addresses: p.a.bobbert@tue.nl (P.A. Bobbert(W.G. van der Wiel).

Peer review under responsibility of Vietnam Nati1 Present address: Raith B.V., De Dintel 27a, 5684 P

https://doi.org/10.1016/j.jsamd.2017.11.0032468-2179/© 2017 The Authors. Publishing services b(http://creativecommons.org/licenses/by/4.0/).

a b s t r a c t

Vertical organic field-effect transistors (VOFETs) provide an advantage over lateral ones with respect tothe possibility to conveniently reduce the channel length. This is beneficial for increasing both the cut-offfrequency and current density in organic field-effect transistor devices. We prepared P3HT (poly[3-hexylthiophene-2,5-diyl]) VOFETs with a surrounding gate electrode and gate dielectric around thevertical P3HT pillar junction. Measured output and transfer characteristics do not show a distinct gateeffect, in contrast to device simulations. By introducing in the simulations an edge layer with a stronglyreduced charge mobility, the gate effect is significantly reduced. We therefore propose that a damagedlayer at the P3HT/dielectric interface could be the reason for the strong suppression of the gate effect. Wealso simulated how the gate effect depends on the device parameters. A smaller pillar diameter and alarger gate electrode-dielectric overlap both lead to better gate control. Our findings thus provideimportant design parameters for future VOFETs.© 2017 The Authors. Publishing services by Elsevier B.V. on behalf of Vietnam National University, Hanoi.

This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).

1. Introduction

Organic field-effect transistors (OFETs) are extensively appliedin low-cost [1], flexible [2], and biocompatible [3] electronic de-vices. It is critical to achieve high cutoff frequencies (~10 MHz) andlarge current densities (10e20 mA/cm2) to improve the deviceperformance for many OFET applications, such as organic light-emitting transistors or display pixel drivers [4e6]. In addition toapplying high-mobility organic semiconductors, this can be ach-ieved by decreasing the OFET channel length [7e9]. Short-channel

p, MESAþ Institute for17, 7500 AE Enschede, The

), w.g.vanderwiel@utwente.nl

onal University, Hanoi.S Best, The Netherlands.

y Elsevier B.V. on behalf of Vietnam

OFETs are also beneficial for low-power electronic applications,since sizeable current densities can be obtained, even operating atlow voltages [10,11].

In typical lateral OFETs, also known as organic thin film tran-sistors (OTFTs), the source and drain electrodes are in the sameplane [12]. Usually, nanolithography techniques or high-resolutionshadow masks are needed to fabricate short spacing electrodes[13e15]. In VOFETs, by contrast, the source is positioned above thedrain, or vice versa, and the current mainly flows vertically. VOFETsare very attractive with respect to down scaling the channel length,since the distance between the top and bottom electrodes can beeasily reduced in organic thin-film technology [7]. Although OFETshave been intensively studied, there are much less reports onVOFETs. Several approaches for realizing VOFETs have already beenreported. Examples include the organic Schottky barrier transistors[7,16e21], the step-edge VOFETs [7,22e28], the interdigitated ver-tical-channel OFETs [6,7], the vertical multichannel organic tran-sistors [7,29], the three-dimensional VOFETs [7,30e33], the central-gate vertical molecular transistors [34], the vertical organic light-

National University, Hanoi. This is an open access article under the CC BY license

Fig. 1. Fabrication of VOFET devices. In each subfigure, the top is a top view and the bottom is a side view of the devices. (a) Fabrication of bottom electrodes (Pd, with Ti as adhesionlayer) on SiO2 substrates by photolithography. (b) Spin-coating of P3HT. (c) Wedging transfer of EBL patterned Pd disks. (d) RIE with O2 ions for pillar formation. (e) ALD of Al2O3. (f)Al gate electrodes patterned by photolithography. (g) Spin-coating of HSQ. (h) CHF3 RIE to open the Al and Al2O3 on top of the Pd top contacts. (i) Ar mechanical ion etching toremove the Al, Al2O3, and partly HSQ, to open the Pd top contacts. (j) Second HSQ spin-coating; (k) CHF3 RIE to open the Pd top contacts. (l) Patterning of large top electrodes byphotolithography and RIE.

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Fig. 2. Colored SEM images showing cross sections of the full-gate (a) and the half-gate (b) test devices: P3HT (100 nm, green), Pd top electrode (150 nm, yellow), Pdbottom electrode (20 nm, yellow), Al2O3 gate dielectric (25 nm, purple), and Al gateelectrode (30 nm, blue).

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emitting transistors (OLETs) [7,35e37] and the vertical OTFTs [38].These vertical devices have different device structures and workingprinciples. Due to the huge variety of device structures, it is chal-lenging to develop a unified working principle for VOFETs, and tocompare between different device configurations.

In this report, the following pillar-shaped VOFET configurationis studied (see Fig. 1). An organic film is sandwiched betweensource and drain electrodes. The gate electrode and dielectric areeither completely surrounding the two-terminal pillar or are onlydeposited from one side. Hence, the channel length is deter-mined by the organic layer thickness. This particular VOFET ge-ometry has to the best of our knowledge not yet beeninvestigated. In this vertical configuration, fabricating contacts ontop of the thin organic film, and patterning of the organic film arechallenging. For the top contacting, the main difficulty is to de-posit the metal contact without damaging the organic film orintroducing an additional resistance or an oxide layer. As for thepatterning, chemicals used in standard nanolithography, e.g.,photolithography and electron beam lithography as well as lift-off processes can affect the organic films [39,40]. In our previ-ous work [4], we have already demonstrated a fabricationmethod that can realize robust vertical P3HT (poly[3-hexylthiophene-2,5-diyl]) pillar devices with ultrashort (downto 5 nm) junction length, and submicron lateral dimensions(down to 200 nm). Following up on that work, we fabricated asurrounding gate electrode and a gate dielectric around thevertical P3HT pillars to add gate control to the electrical trans-port. On applying a voltage to the surrounding gate electrode, weexpect the formation of a conductive channel at the circumfer-ence of the P3HT pillars. We measured output and transfercharacteristics of those novel devices (see Section 3). Numericaldevice simulations using the ATLAS software [43] were per-formed as well (see Section 4).

2. Device fabrication

In this section, the fabrication process of the gated devices isbriefly described. More details are provided in Refs. [4,41]. Thewhole fabrication process is schematically shown in Fig. 1. Weemployed a water-based wedging transfer technique [42] anddirectional oxygen plasma reactive ion etching (RIE) to prepareP3HT pillars with palladium top contacts (Fig. 1(a)e(d)). The P3HTthickness of the gated devices was 100 nm, and the pillars haddiameters d¼ 2 mm,1 mm, 500 nm and 200 nm. Themain differencewith the process described in Ref. [4] is that the Al2O3 gatedielectric and Al gate electrodes were fabricated before applyingthe contact pads of the top electrodes. The conformal Al2O3 gatedielectric was grown by atomic layer deposition (ALD) (Fig. 1(e)).The Al gate electrodes were evaporated and patterned by photoli-thography (Fig. 1(f)).

We found that when the sample straightly faced the evaporationsource during the Al deposition, the overlap of the gate dielectricand the gate electrode around the pillars was very small, as shownin Fig. 2(a). The reason is that the top Pd contact acts as a shadowmask, and suppresses the deposition of Al in the region closelyaround the gate dielectric. Hence, we tilted the sample by 45� suchthat the Al was evaporated from one side. Using this method, wefound that the overlap became larger, as shown in Fig. 2(b). Thedisadvantage is that the gate electrode does not contact the gatedielectric at the other side of the pillar. In the following, the formerdevice type is called “full-gate” and the latter type is called “half-gate”.

After fabrication of the Al gate electrodes, hydrogen silses-quioxane (HSQ) was spin-coated to planarize the sample surface(Fig. 1(g)). After this, CHF3 reactive ion etching (RIE) was used toremove the HSQ on top of the pillars, thereby opening the Al ontop of the pillars (Fig. 1(h)). In the following step, the Al andAl2O3 on top of the pillars were etched away by reactive ionbeam etching (RIBE) with Ar ions (Fig. 1(i)) to expose the top Pdcontacts. At RIE, one has a plasma between two electrodes, witha substrate usually lying on one of the electrodes. The ions collidedue to the small free path length (1 mme1 cm) with other atomsand ions. So one etches with ions and not directionally. At RIBE,one has a plasma between two electrodes whose negative elec-trode is a grid, causing the ions to pass through. The ions arethen accelerated by a negative acceleration voltage and thenneutralized by a neutralizer. The pressure in the room is lowerand the free path length is much larger (a few meters). One thusetches with neutral argon atoms and directionally. Conductive-probe AFM was used to check if the Pd top contacts werecompletely exposed. Once the exposure was verified, we spin-coated a new HSQ layer (Fig. 1(j)) since the first HSQ layer wasalready very thin and not well insulating after the above twosteps of dry etching. Back-etching of the new HSQ layer wasperformed to open the Pd top contacts (Fig. 1(k)). After this step,conductive-probe AFM was used again to check if the HSQ on topof the Pd top contacts was etched away. Finally, large top elec-trodes were deposited and patterned by photolithography andmechanically by RIE (Fig. 1(l)).

3. Electrical characterization

The electrical transport properties of the devices weremeasuredat room temperature (294 K) in a turbo-pumped vacuum(~10�5�10�6 mbar) to suppress the air instability mentioned inRef. [4]. We used a probe station connected with an Agilent B2912Aprecision source/measure unit for these measurement. The bottomPd electrodes were set as the source electrodes, which were alwaysthe common ground.

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Fig. 3 shows the transport characteristics of a half-gate devicewith d ¼ 1 mm P3HT diameter. In Fig. 3(a), the top panel shows ameasurement of the drain current ID when sweeping the source-drain voltage and alternating the gate-source voltage VGS be-tween 10 V and �10 V. The top panel of Fig. 3(b) shows ID as afunction of VGS, at different drain-source voltage VDS. The bottompanels in Fig. 3 show the corresponding gate leakage measure-ments. The results do not show a distinct gate effect, apart from asmall drift of ID when sweeping VGS and keeping VDS constant(Fig. 3(b)). All full-gate and most half-gate devices show similarresults. We also exchanged the source and drain electrodes, that is,we grounded the top Pd electrodes. Again, no distinct gate effectwas observed.

We observed somewhat different IDeVGS results in two devices,one with d ¼ 1 mm and one with d ¼ 200 nm, although the outputproperties of the two devices did not show a distinct gate effect.While measuring transfer characteristics, ID slightly changed withthe gate voltage. Specifically, ID increased when VGS became morenegative. In addition, when VGS was swept from negative to posi-tive, ID decreased, as shown in Fig. 4. Linear fitting reveals that the

Fig. 4. Transfer characteristics of two half-gate devices. Symbols are measured data and grethen to �12 V, and finally back to 0 V. The gate leakage results are similar to Fig. 3(b).

Fig. 3. Output (top panel of (a)) and transfer (top panel of (b)) characteristics of a half-measurement results. (a) VGS was set to 0 (black squares), 10 (red dots), 0 (blue up triangles)from 0 to 2 V, then to �2 V, and finally back to 0 V. (b) VDS was set to 1.75 V (black squares),10 V, then to �10 V and finally back to 0 V.

transconductance ((IDmaxeIDmin)/(VGSmaxeVGSmin), similarly here-after) is 1 pS for VDS ¼ �3 V and 3 pS for VDS ¼ �5 V for the devicewith d ¼ 1 mm (Fig. 4(a)). For the device with d ¼ 200 nm, thetransconductance is only 0.13 pS when VDS ¼ �5 V (Fig. 4(b)). Thetwo devices were measured again before breakdown due to a toolarge gate voltage applied. The weak effect was reproducible. It isnot likely that this weak gate dependence is due to the drift of thedrain current. As shown in Fig. 3(b), the drift of ID is always in onedirection, regardless of the sweep direction of the gate voltage. It isnot likely either that the weak gate dependence is due to theleakage between the gate and the drain. During the measurement,the source was the common ground in the ID and IG measurementcircuits. If there was leakage through the dielectric between thegate and the drain, the IG signal would add to the ID one, therebymaking ID more positive when IG becomes more negative. One cansee in the bottom panel of Figs. 3(b) and 4 that jIGj is getting largerthan jIDjwhen VGS approaches to�10 V. Theweak gate dependenceindicates that there is probably some p-type channel behavior inthe devices, which could be related to the p-type semiconductornature of P3HT. We cannot draw a definite conclusion, however,

en lines are linear fits. (a) d ¼ 1 mm. (b) d ¼ 200 nm. VGS was first swept from 0 to 12 V,

gate device with d ¼ 1 mm P3HT diameter. The bottom panels are corresponding IG, �10 (pink down triangles), and 0 V (green diamonds), respectively. VDS was first swept�1 V (red dots), and �2 V (blue up triangles), respectively. VGS was first swept from 0 to

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because of the small effect, and because it was only observed in twodevices.

In summary, neither of the full-gate and half-gate devicesshowed a significant gate effect. Two half-gate devices showed aweak gate effect. In the following section we discuss device simu-lation results and possible reasons for the absence of a significantgate effect.

Fig. 6. Simulation results for the device with a 200 nm diameter P3HT layer with 73 nmdifferent values of VGS. (b) Transfer characteristics for VDS ¼ �5 V. (c) Hole concentration (loscale) in the region close to the interface when VGS ¼ VDS ¼ �5 V. The rightmost oxide reg

Fig. 5. The 2D cylindrical mesh. (a) Rotation of a 2D rectangle to form a 3D cylinder. (b) Mesource, drain and gate electrodes were set as top, bottom and right boundaries, respectivelyaxis is the distance from the source, which is always at Y ¼ 0 (similarly hereafter). The drawn100 nm, and a thickness of the gate dielectric of 20 nm. All the regions close to the interfaces

4. ATLAS device simulations

We performed numerical device simulations using ATLAS soft-ware [43] to investigate the output and transfer characteristics ofthe gated P3HT pillar devices. The simulations are based on thedrift-diffusion model for electrical transport with a Gaussian den-sity of states (DOS) [44]. Since the pillar structures are radially

gate electrode height and 25 nm oxide thickness. (a) Output characteristics for threeg scale) in the whole P3HT region for VGS ¼ VDS ¼ �5 V. (d) Hole current density (logion is not completely shown here (similarly hereafter).

sh grid on the 2D rectangle. The rightmost part of the rectangle is the gate dielectric;(similarly hereafter). The X axis is the distance from the center of the pillars, and the Ysituation corresponds to a 3D pillar device with P3HT diameter of 2 mm and thickness ofwere finely meshed with a 1 nm mesh size. Other regions were more coarsely meshed.

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symmetric, we employed a 2D cylindrical mesh method to transferthe 3D structure to a 2D structure in order to decrease simulationtime. Fig. 5(a) schematically shows the construction of the 2D cy-lindrical mesh. When a 2D rectangle is rotated by 360� with one ofits sides as the axis of rotation, it forms a cylinder. In this method,only the 2D rectangle needs to be meshed. The simulation resultsfor the rectangle are then rotated to obtain the results in the 3Ddevice (Fig. 5(b)). Although the half-gate devices are not radiallysymmetric, we assume that the gating at only side only implies apartial loss of the gate control. Hence, we used the same meshmethod to simulate the half-gate devices.

We simulated the characteristics of device with d ¼ 200 nmP3HT diameter. We took 25 nm and 73 nm for the gate dielectricthickness and gate electrode height (the vertical length of thecontact area between the gate electrode and the gate dielectric),respectively, according to the SEM image of the half-gate device(Fig. 2(b)). Since we obtained excellent agreement of the modeled

Fig. 7. Discrepancy between simulated and measured results for full-gate and half-gate deaveraged measurement results of all full-gate devices and red solid circles are simulated rtriangles are averaged measurement results of all half-gate devices and blue solid triangles ablack solid squares are simulated results of the non-gated devices. Dashed and solid lines rmeasured results of full-gate (e) and half-gate (f) devices with different P3HT pillar diamet

and the measured results for the two-terminal devices with100 nm P3HT thickness in Ref. [4], we used the same parameters inthe drift-diffusion model incorporated in ATLAS for the devicesimulations in this report. Hence, we set the room-temperature,zero-concentration, zero-field hopping mobility m0 to7� 10�9 m2/Vs, the site density Nt to 1.5 � 1026 m�3, and the widthof the Gaussian DOS s to 0.075 eV. The P3HT dielectric constantεr ¼ 4.4 was taken from Ref. [45].

The simulation results demonstrate a distinct gate effect, asshown in the simulated output and transfer characteristics(Fig. 6(a) and (b)). The hole concentration and hole current densitydistributions demonstrate that the accumulation layer thickness isonly a few nanometers (Fig. 6(c) and (d)). The transconductance isof the order of nS, which is much larger thanwhat we measured inthe devices that showed some gate control (Fig. 4(b)). Further-more, the simulated current is many times larger than themeasured results (Fig. 7(e) and (f)). When V < �3 V, we can see

vices with four different diameters of the P3HT layers. In (a)e(d), red open circles areesults of the full-gate devices (10 nm gate electrode height) at VGS ¼ 0 V; blue openre simulated results of the half-gate devices (73 nm gate electrode height) at VGS ¼ 0 V;epresent the slope k ¼ 1 and k ¼ 2, respectively. (e)e(f) Ratio of the simulated to theers.

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that the ratio of the simulated to the measured drain currents atzero gate voltage decreases when the voltage approaches �5 V.When V > �3 V (smaller negative voltages), the conductivity ofdevices with d¼ 200 nm P3HT diameter is very low. Therefore, themeasured results are very noisy and limited by noise level(Fig. 7(d)), with an unstable ratio that decreases with increasingvoltage (Fig. 7(e) and (f)). Half-gate devices and full-gate devices(with a smaller gate electrode height than the half-gate devices,set as 10 nm in accordance with Fig. 2(a)) with larger diametersthan d ¼ 200 nmwere simulated as well. The simulated results allshow a distinct gate effect. Different from the device withd¼ 200 nm P3HT diameter, the ratio is smaller and decreases frommore than an order of magnitude to a few times when the voltagechanges from �0.2 V to �5 V, as shown in Fig. 7(e) and (f). Thedependence of the ratio on the voltage is related to the differencebetween the simulated and the measured JeV characteristics. InFig. 7(a)e(c), the slope k of the measured logJelogV characteristicsreaches 2 at lower voltages than in the simulated results. In ourdevice, Pd was used for both top and bottom contacts and theinjection barrier is expected to be very low according to our

Fig. 8. 5 nm thick damaged region (the shaded area) close to the interface with theoxide of a half-gate device with d ¼ 200 nm P3HT diameter (73 nm gate electrodeheight and 25 nm oxide thickness). In reality, the damaged region will very likely havea different shape. We assigned a smaller mobility to the damaged region than to theundamaged P3HT. We only modulated the thickness and the mobility of the damagedregion in our analysis.

Fig. 9. Transfer characteristics simulated with and without the damaged layers. (a) Differefactor 0.01: 0 nm (black squares), 5 nm (red dots) and 50 nm (blue up triangles). (b) Damagereduced by a factor 0.1 (blue up triangles), 0.01 (red solid circles), and 0.001 (pink down tr

previous results [4]. For such kind of devices, the slope k ¼ 2 in-dicates the space-charge-limited current (SCLC) regime. Accordingto the SCLC theory, there is usually an ohmic regime where k¼ 1 atsufficiently low voltages [46e48]. Although the simulations andthe measurements in this report did not cover that voltage regimecompletely, we can see in Figs. 7 (a)e(c) that there is a transitionfrom k < 2 to k ¼ 2. In the ohmic regime, the current is due to thethermal equilibrium charge carriers. With increasing voltage,more and more charge carriers are injected into the organic,thereby building up electric potential, and hence limiting thecharge carrier injection. When the injected charge carrier densityexceeds the thermal equilibrium density of charge carriers thathave diffused from the electrodes into the organic layer, the cur-rent changes from ohmic to SCLC. So, the transition voltage atwhich the lines with k¼ 1 and k¼ 2 intersect is proportional to thethermal equilibrium charge carrier density [46,48]. It has beenpointed out that the ohmic regime in such kind of devices is due tothe charge carriers that have diffused from the electrodes into theorganic layer. A smaller transition voltage indicates a smallerthermal equilibrium charge carrier density, leading to a lowercharge carrier mobility [47,49]. Figs. 7(a)e(d) show that the dif-ference between half-gate and full-gate devices is largest for200 nm, both in experiment and simulations, and that this dif-ference vanishes for larger diameter. We suppose this is due to theoverall increase of the effect of gating for the thinnest devices.From the simulation results we conclude that there is not only adifference between simulations and experiments regarding thegate effect, but also regarding the size of the conductivity of thedevices, especially for the device with d ¼ 200 nm P3HT diameter.In the following simulation results, we will show how the mobilityaffects the gate effect and the device conductivity.

Since gate control of transistors is mainly caused by the gener-ation of an accumulation layer in the region close to the semi-conductor/dielectric interface, the reason for the almost absentgate effect in our devices probably lies in the region where theaccumulation layer is supposed to be created. We used directionalO2 plasma RIE to etch the P3HT, but it is very likely that the oxygenions are scattered and spread out. Therefore, the outermost part ofthe P3HT pillars is possibly damaged by the oxygen ions, leading todangling bonds and therefore traps in that region. Even thoughcharge carriers could be accumulated there by the gate field, theywould not freely move. We therefore assume a smaller room-temperature, zero-concentration, zero-field, hopping mobility m0in a thin edge region of the P3HT pillar close to the P3HT/Al2O3interface, as shown in Fig. 8.

nt thicknesses of the damaged layer for a mobility in the damaged layer reduced by ad layer with thickness of 5 nm and unreduced mobility (black squares), and mobilitiesiangles).

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The simulation results shown in Fig. 9 reveal that even a 5 nmdamaged layer with 10% of the mobility of undamaged P3HT canalready significantly suppress the gate effect. The hole current flowin the damaged region is suppressed, but the hole accumulation inthe damaged layer is not significantly affected, as shown in Fig. 10.These simulation results indicate that a damaged layer could indeedbe the cause of the strong suppression of the gate effect. Therefore,to prevent the formation of such a layer in fabrication, using RIE to

Fig. 10. Hole concentration ((a)e(c), log scale) and hole current density ((d)e(f), log scale) inthere is no damaged layer. The damaged layer thickness is 5 nm for (b), (c), (e) and (f). The mand (e), and to 0.001 of this mobility for (c) and (f).

form P3HT pillars is probably not the most suitable method. Weneed to consider alternative methods for the fabrication of VOFETswith a similar structure as described in this report. For example, wecan fill in the pores of an anodic Al2O3 (AAO) template with anorganic semiconductor to form organic-dielectric coreeshell struc-tures [50e52]. The bottom and the surrounding electrodes, and thetop electrodes could be fabricated before and after the fillingrespectively, thereby obtaining organic nanowire transistors [53].

the region close to the organic/dielectric interface, for VGS ¼ VDS ¼ �5 V. In (a) and (d)obility of the damaged layer was set to 0.1 of the mobility of undamaged P3HT for (b)

Fig. 12. Simulated transfer characteristics of three devices with different gate elec-trode height. The devices have a P3HT diameter and oxide thickness of 2 mm and20 nm, respectively. The height of the gate electrodes is 10 nm, 52 nm and 100 nm,respectively, as shown schematically on the top.

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However, both the gate effect and the magnitude of the draincurrent simulated with the damaged layer, either 5 nm thickwith 0.001 � m0 or 50 nm thick with 0.01 � m0, are still largerthan the experimental results. Therefore, we fixed the decreasedmobility at a very low value (10�10 � m0), corresponding to theassumption that the damaged part is completely insulating, andthen changed the thickness of the damaged layer to see whenthe simulated transconductance matches the experimental re-sults. The simulation results reveal that, for the device withd ¼ 200 nm P3HT diameter, when the damaged layer is 81 nmthick, the transconductance drops to about 0.9 pS, which is closeto the experimental result. Moreover, the magnitude of thecurrent is then close to the measured result as well, as shown inFig. 11. Hence, both the weak gate effect and the small current inthe experiment can be explained by assuming a thick damagedlayer. We performed similar simulations for the devices with1 mm P3HT diameter. We find that the thickness of the damagedlayer then has to be about 200 nm to obtain simulation resultsfor the gate effect and the size of the current that are roughlyequal to the measured data. As for the devices with d ¼ 2 mm and500 nm, we find that the damaged layer thickness has to beabout 500 nm and 100 nm respectively, to obtain a roughagreement. These results suggest that the damaged P3HT regionin those devices is very thick. It seems unlikely that RIE can leadto such thick damaged regions. Hence, there are probably otherfactors that lead to a reduction of the gate effect and the current.It has been reported that P3HT OFETs stored in air can beaffected by water and oxygen [54]. The fabrication and storagetime for the gated P3HT devices, the time span between thebeginning of the device fabrication and the measurements, isabout five months for the present gated devices. By contrast, thecorresponding time span for the devices with 100 nm P3HTthickness mentioned in Ref. [4] is about two weeks. Hence, wesuspect that the gated P3HT devices were probably severelyaffected by water and oxygen due to the long fabrication andstorage time.

4.1. Gate electrode height dependence

Fig. 2 shows that the full-gate device has a much smaller gateelectrode height than the half-gate devices. Hence, we examinedthe influence of the height of the gate electrodes on the gate effect.We simulated three devices that all had a d ¼ 2 mm P3HT diameterand a 20 nm oxide thickness, but three different gate electrode

Fig. 11. Simulated transfer characteristic of a device with d ¼ 200 nm P3HT diameter,73 nm gate electrode height, 25 nm oxide thickness and 81 nm damaged regionthickness.

heights: 10 nm, 52 nm and 100 nm, respectively. From Fig. 12 wesee that the gate effect is strengthened when the gate electrodeheight is increased. The hole concentration plots reveal that thestronger gate effect is caused both by a larger hole concentrationaround the source contact at finite gate voltage (Fig. 13(a) and (b))and a stronger depletion of charge carriers around the drain contactat zero gate voltage (Fig. 13(c) and (d)).

4.2. Dependence on the diameter of the P3HT pillars

Also the influence of the diameter d of the P3HT pillars on thegate effect was investigated. We found that even for a gate elec-trode height of 100 nm, that is, a gate electrode fully covering thegate dielectric around the pillars, the source-drain current in theoutput characteristics was still not saturated in devices with a largeP3HT pillar diameter (e.g., d¼ 2 mm)when the source-drain voltagewas larger than the gate voltage (Fig. 14(a)). As the diameter d wasdecreased, the source-drain current became more and more satu-rated for non-zero gate voltage. At zero gate voltage, the source-drain current became smaller and smaller with decreasing d untilit was essentially zero (Fig. 14(b)e(d)). This effect is similar to theshort-channel effect in lateral OFETs [55], resulting from adecreasing channel length. The reason behind this phenomenon isthe dominance of the total current by the bulk SCLC, instead of thechannel conduction. It was reported that limiting the bulk SCLCregion can suppress the short channel effect [56,57]. This is anal-ogous to the situation in the vertical P3HT devices, where thecurrent in the bulk region decreases relatively to that in the channelby decreasing the P3HT pillar diameter. From Fig. 15 we can see thatin the region far (~200 nm) away from the gate dielectric in thedevice with the larger P3HT pillar diameter the hole concentrationdistribution is not affected by the gate voltage. By contrast, in thedevice with the smaller P3HT pillar diameter the distribution in thewhole region is affected by the gate voltage.

4.3. Gate electrode position dependence

Above, we concluded that the higher the gate electrode, thebetter the gate control. But when the gate electrode does notcompletely cover the gate dielectric between source and drain,would it then matter if the gate is close to the source or the drain?Device simulation results show that the gate effect is also

Fig. 13. Hole concentrationdistributions (log scale) in twodevices, zoomed into the region close to theorganic/dielectric interface. (a) 100nmhigh gate electrode,withVGS¼VDS¼�5V.(b) 10 nm high gate electrode, with VGS ¼ VDS ¼ �5 V. (c) 100 nm high gate electrode, with VGS ¼ 0 V, VDS ¼ �5 V. (d) 10 nm high gate electrode, with VGS ¼ 0 V, VDS ¼ �5 V.

Fig. 14. Simulated output characteristics of gated P3HT devices with four different P3HT pillar diameters d. The gate electrode height is 100 nm and the oxide thickness is 20 nm.The gate voltage VGS was fixed at three values: 0 V (blue left triangles), �2.5 V (pink down triangles) and �5 V (green diamonds). In (c), the maximum size of ID at zero VGS isabout �50 pA, while in (d) it is essentially zero (on the order of 10�19 A).

B. Xu et al. / Journal of Science: Advanced Materials and Devices 2 (2017) 501e514510

Fig. 15. Hole concentration (log scale) in the devices corresponding to the simulation results of Fig. 14. (a) d ¼ 2 mm, VGS ¼ �5 V and VDS ¼ �15 V. (b) d ¼ 50 nm, VGS ¼ �5 V andVDS ¼ �15 V. (c) d ¼ 2 mm, VGS ¼ 0 V and VDS ¼ �15 V. (b) d ¼ 50 nm, VGS ¼ 0 V and VDS ¼ �15 V.

B. Xu et al. / Journal of Science: Advanced Materials and Devices 2 (2017) 501e514 511

influenced by the position of the gate electrode when the gateelectrode does not completely cover the dielectric. We simulatedtransfer properties of devices with 10 nm high gate electrodes atdifferent positions: close to the drain, close to the source, and in themiddle between the drain and the source, as shown schematicallyin the top of Fig. 16. The simulated transfer properties reveal that

Fig. 16. Simulated transfer characteristics of three devices with different gate electrodepositions. The three devices have the same P3HT pillar diameter d ¼ 2 mm, the sameoxide thickness of 20 nm, and the same gate electrode height of 10 nm. The position ofthe gate electrode is shown schematically on the top.

devices with a gate in themiddle have the largest transconductance(see main panel in Fig. 16).

To understand this, we compare both the hole concentrationand the hole current density distributions for the three cases.When VGS ¼ �5 V, devices with gate electrodes close to the drainhave the smallest hole concentration around the source(Fig. 17(c)), because the gate electrodes are far away from thesource. A poor accumulation layer results in a small conductivity(Fig. 17(f)). Devices with gate electrodes close to the source havethe largest hole concentration in the accumulation layer aroundthe source (Fig. 17(a)). However, their channel region is fartheraway from the drain than for devices with the gate in the middle(Fig. 17(b)). Therefore, a longer SCLC region is needed to bridge thechannel region and the drain. Eventually, the total conductivity issmaller in the devices with the gate close to the source than in thedevices with the gate in the middle; see the difference betweenFig. 17(d) and (e).

Similarly, when VGS ¼ 0 V, devices with gate close to sourcehave the smallest depletion region around the drain (Fig. 18(a)).Hence, those devices show the largest conductivity (Fig. 18(d)). Asfor devices with the gate close to the drain, although they havethe strongest carrier depletion around the drain, the charge car-riers around the source are the least depleted, because the gateelectrode is further away from the source (Fig. 18(c)) as comparedto the other two types of devices. The charge carrier conductionpath between source and drain is built up as shown in Fig. 18(f).

Fig. 17. Hole concentration (log scale, (a)e(c)) and hole current density (linear scale, (d)e(f)) distribution corresponding to the results of Fig. 16 when VGS ¼ �5 V and VDS ¼ �5 V.Only the region close to the oxide/dielectric interface is shown. (a) and (d): Gate close to source. (b) and (e): Gate in the middle. (c) and (f): Gate close to drain.

B. Xu et al. / Journal of Science: Advanced Materials and Devices 2 (2017) 501e514512

As for the devices with gate in the middle, they have a moderatedepletion around both drain and source (Fig. 18(b)), and eventu-ally the most suppressed conduction close to the interface(Fig. 18(e)).

5. Conclusion

We have fabricated vertical organic field-effect transistors(VOFETs) that consist of pillars of poly[3-hexylthiophene-2,5-diyl](P3HT) with a gate that completely or half surrounds the pillars. Wefound that measured electrical characteristics do not show adistinct gate effect. Only two of our half-gate devices show a weakgate effect. Simulation results of ideal devices show not only adistinct gate effect, but also a larger drain current than in the

experiment. Both the size of the gate effect and the drain currentare dramatically reduced in the simulations by assuming a layer atthe edge of the P3HT pillars that is damaged by the reactive-ionetching. This suggest that a damaged layer could be a reason forthe reduction of the gate effect and the conductivity. To obtain areasonable agreement between simulated and measured results,however, the damaged layer has to be assumed to be very thick.Therefore, we believe that there are also other reasons for thereduction of the gate effect and the conductivity. We suspect thatthe devices were probably severely affected by water and oxygendue to the long fabrication and storage time before the measure-ments. Device simulation results also show that a smaller diameterof the P3HT pillars, a larger overlap of the gate dielectric and gateelectrode both lead to better gate control. In future work on these

Fig. 18. Hole concentration (log scale, (a)e(c)) and hole current density (linear scale, (d)e(f)) distribution corresponding to the results of Fig. 16 when VGS ¼ 0 V and VDS ¼ �5 V.Only the region close to the oxide/dielectric interface is shown. (a) and (d): Gate close to source. (b) and (e): Gate in the middle. (c) and (f): Gate close to drain.

B. Xu et al. / Journal of Science: Advanced Materials and Devices 2 (2017) 501e514 513

VOFETs, the most critical issue is to keep the organic/dielectricinterface as intact as possible during the fabrication. In addition,regions with a large bulk current, small overlap of the gatedielectric and gate electrode, should all be avoided as much aspossible to enhance the gate control.

Acknowledgements

This work was financially supported by the NWO-nano (STW)program, grant no.11470 (W.G. van derWiel), the China Scholarship

Council (grant no. 201206090154) and the Guangdong InnovativeResearch Team Program (No. 2013C102). We thank Martin H.Siekman, Thijs Bolhuis and Johnny G.M. Sanderink for technicalsupport. We thank Dr. Ray J. E. Hueting for fruitful discussions.Wethank Prof. Dr. Guofu Zhou for technical discussion.

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