(Joel)Hdl Assignment 1

8/8/2019 (Joel)Hdl Assignment 1

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M.ENGG IN ELECTRONI CS ENGINEERINGII SEMESTER

HDL DESIGNASSIGNMENT-1

SUBMI TTED ON: 25 t h FEBRUARY 2010

J OEL GEORGE MATH EWSTUDENT ID NO: W200 389 84


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TABLE OF CONTENTS

1. Task . 3

2. Ful l adder Design. 4

2.1. In t roduc t ion t o t he design 4

2.2. VHDL Code 4

2.2.1. Bot t om level VHDL Code 5

2.2.2. Bot t om level t est benc h VHDL Code 6

2.2.3. RTL Sc hem at ic 9

2.2.4. Tim ing Diagram 10

Pre-synt hesis t im ing diagram 10

Post -synt hesis t im ing diagram 11

3. 2-1Mul t ip lex er Design. 12

3.1. In t roduc t ion t o t he design. 12

3.2. VHDL Code 13

3.2.1. Bot t om level VHDL Code 13

3.2.2. Bot t om level Test benc h VHDL Code 14

3.2.3. Bot t om level Tim ing Diagram 16

3.2.4. Top level VHDL Code 16

3.2.5. Top level Test benc h VHDL Code 17

3.2.6. Top level Tim ing Diagram 20

Pre-synt hesis t im ing d iagram 20

Post -synt hesis t im ing d iagram 20

3.2.7. RTL Sc hem at ic 21

3.2.8. Im plem ent at ion of t he design 23

4. Referenc e. 25


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1.TASK

PART 1: FULL ADDER. Capture a design for a full adder.

Simulate the design pre and post synthesis.

View the RTL schematic and confirm its structure.

Submit a report containing an introduction to the design, HDL code, pre and post

synthesis timing diagrams and RTL schematic.

PART 2: 2-1 MULT IPLEXERPerform design entry for a 2-1 Mux to be implemented on the Spartan-3 board. Each input

and output has 2 bit. For testing connect the select switch SW7 and each 2 bit input to

switches SW3, SW2 and SW1, SW0. The 2 bit output should be displayed on LEDs LD7

and LD6.

Hierarchical design is to be employed. A top level interface program and bottom level

Mux implementation program to be created.

Simulation test benches for each level to be generated.

Simulate at both levels of the design hierarchy.

Synthesise the design.

Implement the design on the Spartan 3 board and verify the operation.

Submit a report containing an introduction to the design, HDL code, pre and post

synthesis timing diagrams and RTL schematic.


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2. FULL ADDER DESIGN2.1. INTRODUCTION TO THE DESIGN.A full addercircuit is an arithmetic circuit block that can be used to add three bits (A, B,Cin) to produce a SUM (S) and a CARRY output (Co).

A S

B

Cin Co

The truth table of a full adder circuit showing all possible input combinations and

corresponding outputs is given below;

A B Cin S Co0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Truth table of full adder

In order to arrive at the logic circuit for hardware implementation of a full adder, we will

firstly write the Boolean expressions for the two output variables, that is, the SUM (S) andCARRY output (Co), in terms of input variables. The Boolean expressions for the two output

variables are given in Equation below for the SUM output (S) and the CARRY output

(Cout)

FULL A DDER


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After further simplification, the above two expressions can be written as below;

S = (A B) Cin

Cout = (A . B) + (Cin . ( A B))

Therefore, the Sum (S) can be implemented with a two-input EX-OR gate provided that one

of the inputs is Cin and the other input is the output of another two-input EX-OR gate with

A and B as its inputs. Similarly, the Carryout (Co) can be implemented by OR ing two

minterms. One of them is the AND output ofA and B. The other is also the output of an

AND gate whose inputs are Cin and the output of an EX-OR operation on A and B. This is

pictured as shown,

Fig: Full Adder

2.2. VHDL CODEIn this VHDL code, the inputs are referred to as Inp0, Inp1 and the outputs as Cout,

S respectively.

2 .2 .1 . Bo t tom l eve l VHDL Code .

The behaviour of the full adder is described in the bottom level VHDL code. I consist of data

flow which describes how data moves through the system. The data flow makes use of

concurrent statements that are executed in parallel as soon as data arrives at the input.


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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity FullAdder is

Port ( Inp0 : in STD_LOGIC;

Inp1 : in STD_LOGIC;

Ci : in STD_LOGIC;

S : out STD_LOGIC;

Co : out STD_LOGIC);

end FullAdder;

architecture Behavioral of FullAdder is

begin

S


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Ci : IN std_logic;

S : OUT std_logic;

Co : OUT std_logic

);

END COMPONENT;

for uut : FullAdder use entity work.FullAdder;

--Inputs

SIGNAL INP0 : std_logic;

SIGNAL INP1 : std_logic;SIGNAL CI : std_logic;

--Outputs

SIGNAL SUM : std_logic;

SIGNAL CO : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: FullAdder PORT MAP(INP0,INP1,CI,SUM,CO);

tb : PROCESS

BEGIN

--CASE 0:0+0 with carry in of 0.

INP0


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--CASE 3:0+1 with carry in of 1.

INP0


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2 .2 .3 . RTL SCHEMATIC

The RTL schematic consists of collection of gates and components that are interconnected to

perform a desired function. The RTL schematics of the above bottom level VHDL code

(section 2.2.1) are as below:


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2 .2 .4 . T IMING DIAGRAM

The timing diagram or the waveform is obtained as result of running the test bench VHDL

code. It helps us check the whether the behaviour of the VHDL code is working properly or

not. The timing diagram of the full adder is shown below:

1. Pre-synthesis Timing diagram


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2. Post-synthesis timing diagram


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3. 2-1 MULTIPLEXER DESIGN3.1. INTRODUCTION T O THE DESIGNA multiplexerorMUX, also called a data selector, is a combinational circuit which consists

of multiple-input and single-output line and more than one selection line. A multiplexer

selects binary information present on any one of the input lines, depending upon the logicstatus of the selection inputs, and routes it to the output line. If there are n selection lines,

then the number of maximum possible input lines is 2n

and the multiplexer is referred to as a

2n

-to-1 multiplexer or 2n

1 multiplexer.

The schematic of a 2-to-1 multiplexer is shown below. It consists of parallel two input

pins (A and B) and containing the output pin (O). The select (SEL) wire connects the

desired input to the output.

Fig: 2-1 Multiplexer.

The 2-1 Multiplexer circuit functions as follows:

IfSEL = 0 then the output (O) will follow first input (A) and the second input (B) is a don't

care, i.e. it has no influence on the output.

IfSEL= 1 then the output (O) will follow second input (B) and the first input (A) is a don't

care.

Truth table

A(0) A(1) B(0) B(1) O(0) O(1)

S=0 0 0 0 0 0 0

0 1 0 1 0 1

1 0 1 0 1 0

1 1 1 1 1 1

S=1 0 0 0 0 0 0

0 1 0 1 0 1

1 0 1 0 1 0

1 1 1 1 1 1


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The complete Boolean expression and its logic diagram of 2-1 MUX is shown below,

3.2. VHDL CODES

In this VHDL code, the inputs are represented as IN0 and IN1, the output is orOUT

and the select is Sel. In this project, each input of the MUX is having 2bit length and so as

the output. Therefore IN0 (0), IN1 (0) and orOUT (0) are the LSB of the inputs and

output respectively and IN0 (1), IN1 (1), and orOUT (1) are the MSB of the inputs and

output respectively.

3 .2 .1 . BOTTOM LEVEL VHDL CODE

library IEEE;


use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Muxlowlevel is

Port ( andIN0 : in STD_LOGIC_VECTOR(1 downto 0);

andIN1 : in STD_LOGIC_VECTOR(1 downto 0);

Sel : in STD_LOGIC;orOUT : out STD_LOGIC_VECTOR(1 downto 0));

end Muxlowlevel;

architecture Behavioral of Muxlowlevel is

begin

process(andIN0,andIN1,Sel)


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begin

if (Sel='0')then

orOUT(0) andIN1,

Sel => Sel,

orOUT => orOUT

);


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--Apply input stimulus.

STIM : PROCESS ---excecutes the start of the simulation

BEGIN

andIN0(0)


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andIN0(0)


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level VHDL code; IN0(0), IN0(1), IN1(0), IN1(1) are connected to the switches SW(0),

SW(1), SW(2), SW(3) and the outputs orOUT(0), orOUT(1) to the LEDs LED(6),

LED(7) respectively. Its top level VHDL code is as below:

library IEEE;


use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Muxhighlevel is

Port ( SW : in STD_LOGIC_VECTOR (3 downto 0);

SW7 : in STD_LOGIC;

LED : out STD_LOGIC_VECTOR (7 downto 6));

end Muxhighlevel;

architecture combinational of Muxhighlevel is

COMPONENT Muxlowlevel is

port (andIN0, andIN1 : in std_logic_vector(1 downto 0);

Sel : in std_logic;

orOUT : out std_logic_vector(1 downto 0)

);

end COMPONENT;

begin

--Muxlowlevel instance,using named signal association.

Instance_Muxlowlevel: Muxlowlevel PORT MAP

(andIN0(0)=> SW(0),andIN0(1) => SW(1),andIN1(0)=>

SW(2),andIN1(1)=>SW(3),Sel => SW7,

orOUT(0) => LED(6),orOUT(1)=> LED(7));

end combinational;

3.2.5. TOP LEVEL TEST BENCH VHDL CODE.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY Muxhighlevel_TB IS

END Muxhighlevel_TB;

ARCHITECTURE behavior OF Muxhighlevel_TB IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT Muxhighlevel

PORT(


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SW : IN std_logic_vector(3 downto 0);

SW7 : IN std_logic;

LED : OUT std_logic_vector(7 downto 6)

);

END COMPONENT;

--Inputs

SIGNAL SW7 : std_logic := '0';

SIGNAL SW : std_logic_vector(3 downto 0) := (others=>'0');

--Outputs

SIGNAL LED : std_logic_vector(7 downto 6);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: Muxhighlevel PORT MAP(

SW => SW,

SW7 => SW7,

LED => LED

);

STIM: PROCESS

BEGIN

SW(0)


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SW7


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3.2.6. TOP LEVEL TIMI NG DIAGRAMS.

Fig: Pre-synthesis timing diagram

Fig: Post-synthesis timing diagram


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3.2.7. RTL SCHEMATIC OF 2-1 MUX .


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3.2.8. IMPLEMENTING THE DESIGN

Assigning Pin Location Constraints

Specify the pin locations for the ports of the design so that they are connected correctly on

the Spartan-3 Startup Kit demo board. Run the Implement Design processes and make sure

that all of them have green tick mark next to them as shown in the figure below, indicatingthat all of them are up-to- date.


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Download Design to the Spartan-3 Demo Board

The VHDL is downloaded to the Spartan -3 board through iMPACT process.When programming is complete, the Program Succeeded message is displayed.

On the board, LEDs 6 and 7 are lit by giving input values as per the truth table indicating

that the MUX is running.


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4. REFERENCE

(i). VHDL Made Easy.

By, David Pellerin & Douglas Taylor.

(ii). VHDL Programming by Example.By, Douglas L.Perry.

(iii). VHDL-primer.

By, J. Bhaskar.

(iv). www.appliedvhdl.com

(Joel)Hdl Assignment 1

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