Joal 2003 HT:1 Custom Designed Integrated Circuits Em3 1 WeekLectureRefExerciseLab 1/W35Introduction...

joal 2003 HT:1 Custom Designed Integrated Circuits Em3

1

Week Lecture Ref Exercise Lab

1/W35 Introduction to ASIC.Concurrent VHDL

Chap1-3

Chap 3: 3, 4, 5, 10, 13, 14

Lab 1, Concurrent VHDL

2/W36 Sequential VHDL Chap 4 Chap 4: all Lab 2, Sequential VHDL

3/W37 Library, structural VHDL. Statemachines FSM,

Chap 5, 6, 9 Chap 5: 4,7,8,9Chap 6: 1,2,6Chap 9: 1,2,4,5,9

Lab 3State machines

4/W38 File IO, Test benches, Introduction to project.

Chap 8 Chap 8: 1,3,4,5 Lab 4Test benches

5/W39 Project. Chap 7,12, 10,14

Project

6/W40 Design tools. Test. Coding style Design hints. . RTL-syntesis.

Chap 13,15,16 Project

7/W41 Behavioural synthesis. SoC. ASIC technology.

Chap 17 Project

W42 Exam. 15/10


2

Project

The purpose of the project is:

• To use VHDL to do a circuit design that is suitable to implement in a FPGA.

• To use structured design methods.

• To use simulations to verify the design. (Test benches).

• To synthesize the VHDL code.

• To test the designed circuit (FPGA) in a microcontroller environment.


3

ProjectThe students can choose one of two assignments:

• UART (Universal Asynchronous Receiver Transmitter) interfaced to a PIC16F84 microcontroller.

• VGA controller interfaced to PIC16F628

• The interface between the microcontroller and the project circuit is specified.

• The program in the microcontroller is specified and implemented.


4

Project, Test hard ware

FPGAXCS10

OS

C

MA

X232

PIC

16F84

DSUB9

JTA

G

IO-port

RE

G

+ -

DS

UB

15


5

Project, Test hardware

Hyperterminal>?

FPGAXCS10

OS

C

MA

X232 P

IC16F

84

DSUB9

JTA

G

IO-port

RE

G

+ -

DS

UB

15

VGA-monitor


6

ProjectDesign steps:

Design the selected circuit.

Design a test bench.

Verify the design.

Demonstrate the test bench simulations for the supervisor.

Synthesize the circuit and implement it in the test hardware.

Test the design.

Demonstrate the implemented design for the supervisor.

Write a project report and hand it over to the supervisor.


7

ProjectAssignment reports:

Demonstrate the test bench simulations for the supervisor. Every student must be prepared to demonstrate and explain the simulations and to describe the circuit design and the test bench.

Demonstrate the implemented design for the supervisor.

Write a project report and hand it over to the supervisor.

Passed exam for the project

Gate

Gate

Gate


8

Project UART

--************************************************************* -- Project: uart-- clk: input clock 4 MHz. The same clock is used for FPGA and-- microcontroller.-- reset: internal signal in FPGA-- wr: write signal from micro.-- rd: read signal from the micro. dbus direction from FPGA to micro when-- ’1’. Statusreg or datareg on dbus when rd=’1’.-- a0-a1: register selection address lines-- dbus: bidirectonal data bus. (D0 to D7 in schematics)--*************************************************************entity uart is port(clk, reset, wr, rd, a0, a1: in std_logic; dbus: inout std_logic_vector(7 downto 0);end;


9

Project

--************************************************************* -- Project: uart-- duplex: full-- Bitrate: 9600 bits/s. Fix baudrate generator 4 MHz to 9600.-- Data bits: 8-- Parity: even-- Stop bits: 2-- Receiver: Oversampling 16 times-- Clock: 4 Mhz-- Address 0: Data register-- Address 1: Statusregister-- Address X: address 2-7 not used.-- Buffers: Only single buffers => write directly to transmit-- shift register and read directly from receive shift register.--*************************************************************


10

Project

start d0lsb

d1 d2 d3 d4 d5 d6 d7msb

par stop stop

Micro

Receive

Status

Transm

it

FSM


11

Projectstatusreg(0)(a0=’1’,a1-a2=’0’)

Receiver ready reset when data is read from receive-register

statusreg(1) (a0=’1’,a1-a2=’0’)

Transmitter ready reset when data is put into transmit-register

statusreg(2) (a0=’1’,a1-a2=’0’)

Parity error reset when correct parity received

Receivereg(a0-a2=’0’)

8 bit data register

Transmitreg(a0-a2=’0’)

8 bit data register


12

Project

clk

data

wr


13

Projectclk (micro and UART)

data is latched in transmitter

WR

synchronized WR


14

Projectclk (micro and UART)

RD

dbus<=receivereg when rd=’1’ and a0=’0’ else statusreg when rd=’1’ and a0=’1’ else (others=>’Z’);


15

Pattern and style in Project

Design methodology for project

• Don’t build too small or too big entities. (In the project ca 3-5)

• Max 4 levels in hierachi. Structural VHDL is not so easy to understand.

• Use state machines (required).

• Use variables only for temporary storage e.g. in algorithms.

• Never use variables for e.g. registers.

• Use patterns. Look for design examples. A state machine template is an example of

a pattern that can improve the design and the readability.


16

Project VGA Controller

HSYNC

VSYNC

x

y

Cursor-sprite 8*8

Cursorpos(xc, yc)


17

Project VGA ControllerHSync

Timing control VSync

Spritecontrol

Blanking

6 DA

3 VGA

clk

reset

Background sprite

X(9 downto 0)

Cursor sprite

Xbs(2 downto 0)

Ybs(2 downto 0)

Y(8 downto 0)

Xcs(2 downto 0)

Ycs(2 downto 0)

C interface

PIC16F628


18

Project VGA Controller

HSYNC

VSYNC

x

y

Character Generator ROM 8*8*1Box 12*12

RAM pos(xcr, ycr)


19

Project VGA ControllerTiming control

HSync

VSync

Memorycontrol

6

DA3 VGA

clk

reset

Character Memory (RAM)8*8*4

X(9 downto 0)

cgy(2 downto 0)

cgx(2 downto 0)

Y(9 downto 0)

C interface

Character Generator

(ROM)

Blanking

VBlank HBlank

dbus

wr

rd

a0-a2 Xcm(2 downto 0)Ycm(2 downto 0)wr_char

DATA_CM( 3 downto 0)

cg_char( 3 downto 0)

Color Memory (RAM)8*8*2

cg_col( 1 downto 0)

wr_col

PIC16F628

Joal 2003 HT:1 Custom Designed Integrated Circuits Em3 1 WeekLectureRefExerciseLab 1/W35Introduction...

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Transcript of Joal 2003 HT:1 Custom Designed Integrated Circuits Em3 1 WeekLectureRefExerciseLab 1/W35Introduction...